 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| april 2007 rev 1 1/85 1 STW5098 dual low power asynchronous stereo audio codec with integrated power amplifiers features dual 20 bit audio resolution, 8khz to 96khz independent rate adc and dac dual i 2 s or pcm digital interfaces for dual master sustain complex voice and audio flow with or without mixing i 2 c/spi compatible control i/f asynchronous sampling adc and dac: they do not require oversampled clock and information on the audio data sampling frequency (fs). jitter tolerant fs wide master clock range: from 4mhz to 32mhz stereo headphones drivers, handsfree loudspeaker driver, line out drivers mixable analog line inputs voice filters: 8/16khz with voice channel filters automatic gain control for microphone and line- in inputs frequency programmable clock outputs multibit ? modulators with data weighted averaging adc and dac dsp functions for bass-treble-volume control, mute, mono/stereo selection, voice channel filters, de-emphasis filter and dynamic compression 93 db dynamic range adc, 0.001% thd with full scale output @ 2.7v 95 db dynamic range dac, 0.02% thd performance @ 2.7v over 16 ? load applications digital cellular telephones with application processor such as mp3 or gaming and bluetooth concurrent application description STW5098 is a dual low power asynchronous stereo audio codec device with headphones amplifiers for high quality audio listening and recording. two i2s/pcm digital interfaces are available, one per master for example bluetooth and application processor, enabling concurrent audio and voice flow between network and user. the STW5098 control registers are accessible through a selectable i 2 c-bus compatible or spi compatible interface. STW5098 vfbga 5x5x1 (112 pins) lfbga 6x6x1.4 (112 pins) www.st.com
contents STW5098 2/85 contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 naming convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3 device programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.4 power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.5 master clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.6 data rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.7 clock generators and master mode function . . . . . . . . . . . . . . . . . . . . . . 20 4.8 audio digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.9 analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.10 analog output drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.11 analog mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.12 ad paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.13 da paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.14 analog-only operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.15 automatic gain control (agc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.16 interrupt request: irq pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.17 headset plug-in and push-button detection . . . . . . . . . . . . . . . . . . . . . . . 26 4.18 microphone biasing circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.1 summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2 supply and power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.3 gains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.4 dsp control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.5 analog functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 STW5098 contents 3/85 5.6 digital audio interfaces master mode and clock generators . . . . . . . . . . . 41 5.7 digital audio interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.8 digital filters, software reset and master clock control . . . . . . . . . . . . . . . 45 5.9 interrupt control and control interface spi out mode . . . . . . . . . . . . . . . . 46 5.10 agc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6 control interface and master clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.1 control interface i2c mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.2 control interface spi mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.3 master clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7 audio interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8 timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9 operative ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.2 operative supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.3 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.4 typical power dissipation by entity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 10 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.1 digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.2 amck with sinusoid input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.3 analog interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 10.4 headset plug-in and push-button detector . . . . . . . . . . . . . . . . . . . . . . . . 64 10.5 microphone bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 10.6 power supply rejection ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 10.7 ls and ear gain limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 11 analog input/output operative ranges . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.1 analog levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.2 microphone input levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 11.3 line output levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 11.4 power output levels hp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 contents STW5098 4/85 11.5 power output levels ls and ear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 12 stereo audio adc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 13 stereo audio dac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 14 ad to da mixing (sidetone) specifications . . . . . . . . . . . . . . . . . . . . . . 71 15 stereo analog-only path specifications . . . . . . . . . . . . . . . . . . . . . . . . 72 16 adc (tx) & dac (rx) specifications with voice filters selected . . . . . 73 17 typical performance plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 18 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 18.1 lfbga 6x6x1.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 18.2 vfbga 5x5x1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 19 application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 20 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 21 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 STW5098 list of tables 5/85 list of tables table 1. STW5098 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 2. control register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 3. cr0 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 4. cr1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 5. cr2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 6. cr3 and cr4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 7. cr5 and cr6 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 8. cr7 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 9. cr8 and cr9 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 10. cr10 and cr11 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 11. cr12 and cr13 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 12. cr14 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 13. cr15 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 14. cr16 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 15. cr17 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 16. cr18 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 17. cr19 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 18. cr21-20 and cr24-23 description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1 table 19. cr22 and cr25 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 20. cr26 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 21. cr27 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 22. cr28 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 23. cr29 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 24. cr30 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 25. cr31 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 26. cr32 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 27. cr33 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 28. cr 34 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 29. cr 35 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 30. control interface timing with i2c format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 31. control interface signal timing with spi format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 32. amck timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 33. audio interface signal timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 34. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 35. operative supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 36. power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 37. typical power dissipation, no master clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 38. typical power dissipation with master clock amck = 13 mhz . . . . . . . . . . . . . . . . . . . . . . 61 table 39. digital interfaces specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 40. amck with sinusoid input specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 41. analog interface specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 42. headset plug-in and push-button detector specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 43. microphone bias specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 44. power supply rejection ratio specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 table 45. ls and ear gain limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 46. reference full scale analog levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 47. microphone input levels, absolute levels at pins connected to preamplifiers . . . . . . . . . . . 66 table 48. microphone input levels, absolute levels at pins connected to the line-in amplifiers . . . . . 66 list of tables STW5098 6/85 table 49. absolute levels at olp/oln, orp/orn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 50. absolute levels at hpl - hpr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 51. absolute levels at 1earp-1earn and 2lsp - 2lsn. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 52. stereo audio adc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 53. stereo audio dac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 54. ad to da mixing (sidetone) specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 55. stereo analog-only path specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 56. adc (tx) & dac (rx) specifications with voice filters selected. . . . . . . . . . . . . . . . . . . . . 73 table 57. dimensions of lfbga 6x6x1.4 112 4r11x11. 0.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 58. dimensions of vfbga 5x5x1.0 112 balls 0.4 mm pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 59. order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 60. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 STW5098 list of figures 7/85 list of figures figure 1. pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 2. STW5098 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 3. power up block diagram: example shown for one entity . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 4. plug-in and push-button detection application note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 5. control interface i2c format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 6. control interface: i2c format timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 7. control interface spi format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 8. control interface: spi format timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 9. audio interfaces formats: delayed, left and right justified . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 10. audio interfaces formats: dsp, spi and pcm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 11. audio interface timings: master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 12. audio interface timing: slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 13. a.c. testing input-output waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 14. bass treble control, de-emphasis filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 15. dynamic compressor transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 figure 16. adc audio path measured filter response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 17. adc in band audio path measured filter response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 18. dac digital audio filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 19. dac in band digital audio filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 figure 20. adc 96 khz audio path measured filter response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 21. adc 96 khz audio in-band measured filter response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 22. adc voice tx path measured filter response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 23. adc voice tx path measured in-band filter response . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 24. dac voice (rx) digital filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 25. dac voice (rx) in-band digital filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 26. adc path fft. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 27. adc s/n versus input-level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 28. dac path fft. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 29. dac s/n versus input-level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 30. analog path fft . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 31. analog path s/n versus input-level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 32. lfbga 6x6x1.4 112 4r11x11 0.5 drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 33. vfbga 5x5x1.0 112 0.4 drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 34. STW5098 application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 overview STW5098 8/85 1 overview dual 20 bit audio resolution, 8khz to 96khz independent rate adc and dac dual i 2 s/pcm digital interfaces for dual master sustain complex voice and audio flow with or without mixing tw o i 2 c/spi compatible independent control interfaces asynchronous sampling adc and dac that do not require oversampled clock and information on the audio data sampling frequency (fs). jitter tolerant fs wide master clock range from 4mhz to 32mhz two stereo headphones drivers, hand free loudspeaker driver, line out drivers mixable analog line inputs voice filters: 8/16khz with voice channel filters automatic gain control for microphone and line-in inputs four programmable master/slave serial audio data interfaces: i 2 s, spi, pcm compatible and other formats frequency programmable clock outputs multibit ? modulators with data weighted averaging adc and dac four dsp functions for bass-treble-volume control, mute, mono/stereo selection, voice channel filters, de-emphasis filter and dynamic compression 93 db dynamic range adc, 0.001% thd with full scale with full scale output @ 2.7v 95 db dynamic range dac, 0.02% thd performance @ 2.7v over 16 ? load analog inputs selectable stereo differential or single-ended microphone amplifier inputs with 51db range programmable gain 2 microphone biasing output microphone plug-in and push-button detection input selectable stereo differential or single-ended line inputs with 38db range programmable gain analog output drivers 2 stereo headphones outputs. driving capability: 40mw (0.1% thd) over 16 ? with 40db range programmable gain common mode voltage headphones driver (phantom ground) 1 balanced loudspeaker output with driving capability up to 500m w (v ccls >3.5v; 1% thd) over 8 ? with 30db range programmable gain 1 balanced earphone output with driving capability up to 125m w transient suppression filter during power up and power down balanced/unbalanced stereo line outputs with 1 k ? driving capability STW5098 pinout 9/85 2 pinout figure 1. pin assignment gnd 2sclk 1hdet 1micln 1aux1l 2aux1l 1miclp 2capmic 1lineinl 1aux2lp 2aux2lp 1olp gndcm vccp 1hpl 2hpl 1earps 2vcmhp 1vcmhp gndp 1capear 2capls gndp 1earp 1earns 2lsns 1hpr 2orp 1da_data 1irq 2mbias vcca 2aux1r 1micrn 2micrn 1caplinein 2micrp 2aux2rn 1aux2rn 2aux2rp 1lineinr 2orn gndp vcca 2ad_ock 1ad_ock 1cmod vccio 2da_ock 1da_ock 1da_ck 2da_ck 1ad_data amck 1as/csb 2ad_sync 1ad_sync 2da_data 2hdet 2micln 1aux3l 2aux3l 1capmic gnda 1aux2ln 2lineinl 2aux2ln 2oln 1oln gndcm vccp 2olp vcc 1sclk 2cmod 2sda/sdin 1sda/sdin 2ad_ck 1ad_ck 2as/csb 2ad_data vcc 2da_sync 2irq gnd 1da_sync 1mbias 1aux1r 2caplinein 2aux3r 1micrp 1aux3r 1aux2rp gnda 2lineinr 1orn 1orp gndp 1vcmhps 2vcmhps vccls 2lsps 2lsp vccp 1earn 2lsn vccls vccls vccp 2hpr 2miclp vcca 1234567891011 a b c d e f g h j k l pinout STW5098 10/85 table 1. STW5098 pin description position type pin name description a1 p gnd ground pin for the digital section a2 di 1sclk control interface serial clock input a3 do 1ad_ock oversampled clock out from ad clock generator a4 diod 2sda/sdin control interface serial data input-output in i 2 c mode (sda), control interface serial data input in spi mode (sdin). a5 do 1da_ock oversampled clock out from da clock generator a6 dio 1ad_ck serial data clock for stereo a/d converter a7 di 2as/csb control interface address select in i 2 c mode (as). interface enable signal in spi mode (csb). a8 do 2ad_data serial data out for stereo a/d converter a9 dio 2ad_sync frame sync for stereo a/d converter a10 dio 1da_sync frame sync for stereo d/a converter a11 di 1da_data serial data in for stereo d/a converter b1 ai 2hdet headset detection input (microphone plug-in and push-button detection) b2 di 2sclk control interface serial clock input b3 do 2ad_ock oversampled clock out from ad clock generator b4 di 1cmod control interface type selector i 2 c-bus mode or spi mode b5 do 2da_ock oversampled clock out from da clock generator b6 dio 2da_ck serial data clock for stereo d/a converter b7 di ai amck master clock input. accepted range 4 mhz to 32 mhz. amck is a digital square wave amck is an analog sinewave ( section 10.2 on page 62 ) b8 p vcc power supply pin for the digital section. operating range: from 1.71 v to 2.7 v b9 dio 2da_sync frame sync for stereo d/a converter b10 di 2da_data serial data in for stereo d/a converter b11 p gnd ground pin for the digital section c1 p vcca power supply pin for the analog section. standard operating range: from 2.7v to 3.3v low voltage (lv) range: from 2.4v to 2.7v c2 ai 1hdet headset detection input (microphone plug-in and push-button detection) c3 p vcca power supply pin for the analog section. standard operating range: from 2.7v to 3.3v low voltage (lv) range: from 2.4v to 2.7v c4 di 2cmod control interface type selector i 2 c-bus mode or spi mode. STW5098 pinout 11/85 c5 diod 1sda/sdin control interface serial data input-output in i 2 c mode (sda). control interface serial data input in spi mode (sdin). c6 dio 2ad_ck serial data clock for stereo a/d converter c7 do 1ad_data serial data out for stereo a/d converter c8 dio 1ad_sync frame sync for stereo a/d converter c9 do 2irq programmable interrupt output. active low signal. c10 ao 2mbias microphone biasing pin. fixed voltage reference c11 ao 1mbias microphone biasing pin. fixed voltage reference d1 ai 2aux1l left and right channel single ended pins for microphone or line input d2 ai 1aux1l left and right channel single ended pins for microphone or line input d3 ai 1micln left and right channel differential pins for microphone input d4 p vcc power supply pin for the digital section. operating range: from 1.71v to 2.7v d5 p vccio power supply pin for the digital i ? o buffers. operating ranges: from 1.2v to 1.8v and from 1.71v to v cc d6 dio 1da_ck serial data clock for stereo d/a converter d7 di 1as/csb control interface address select in i 2 c mode (as) interface enable signal in spi mode (csb) d8 do 1irq programmable interrupt output. active low signal. d9 p vcca power supply pin for the analog section. standard operating range: from 2.7v to 3.3v low voltage (lv) range: from 2.4v to 2.7v d10 ai 1aux1r left and right channel single ended pins for microphone or line input d11 ai 2aux1r left and right channel single ended pins for microphone or line input e1 ai 2aux3l left and right channel single ended pins for microphone or line input e2 ai 1aux3l left and right channel single ended pins for microphone or line input e3 ai 1miclp left and right channel differential pins for microphone input e4 ai 2micln left and right channel differential pins for microphone input e8 ai 2caplinein a capacitor must be connected between caplinein and ground e9 ai 1micrn left and right channel differential pins for microphone input e10 ai 2aux3r left and right channel single ended pins for microphone or line input e11 ai 2micrn left and right channel differential pins for microphone input f1 ai 2capmic a capacitor must be connected between capmic and ground. f2 ai 1capmic a capacitor must be connected between capmic and ground f3 p gnda ground pin for the analog section f4 ai 2miclp left and right channel differential pins for microphone input table 1. STW5098 pin description position type pin name description pinout STW5098 12/85 f8 ai 1caplinein a capacitor must be connected between caplinein and ground f9 ai 1micrp left and right channel differential pins for microphone input f10 ai 1aux3r left and right channel single ended pins for microphone or line input f11 ai 2micrp left and right channel differential pins for microphone input g1 ai 1aux2ln left and right channel differential pins for microphone or line input g2 ai 2aux2ln left and right channel differential pins for microphone or line input g3 ai 1lineinl left and right channel single ended pins for line input g4 ai 2lineinl left and right channel single ended pins for line input g8 p gnda ground pin for the analog section g9 ai 1aux2rp left and right channel differential pins for microphone or line input. g10 ai 1aux2rn left and right channel differential pins for microphone or line input g11 ai 2aux2rn left and right channel differential pins for microphone or line input h1 ai 1aux2lp left and right channel differential pins for microphone or line input h2 ai 2aux2lp left and right channel differential pins for microphone or line input h3 ao 2oln audio differential line out amplifier for left and right channels. this outputs can drive up to 1k ? resistive load. can be used as single ended output. h4 p gndcm ground pin for analog reference. gndcm can be connected to gnda h5 ao 1earps earps, earns (sense) pins must be connected on the application board to earp, earn pins respectively. the connection must be as close as possible to the pins. h6 ao 1earp analog differential loudspeaker amplifier output for left channel or right channel or the sum of both. this output can drive 50nf (with series resistor) or directly an earpiece transductor from 8 ? . to 32 ? . can deliver from 500mw to 125mw. h7 p vccp power supply pin for the left and right output drivers (headphones and line-out). operating range: from v cca to 3.3v h8 ao 1hpr audio single ended headphones amplifier outputs for left and right channels. the outputs can drive 50nf (with series resistor) or directly an earpiece transductor of 16 ? . h9 ao 2orn audio differential line out amplifier for left and right channels. this outputs can drive up to 1k ? resistive load. can be used as single ended output. h10 ai 2lineinr left and right channel single ended pins for line input h11 ai 2aux2rp left and right channel differential pins for microphone or line input j1 ao 1oln audio differential line out amplifier for left and right channels. this outputs can drive up to 1k ? resistive load. can be used as single ended output. table 1. STW5098 pin description position type pin name description STW5098 pinout 13/85 j2 ao 1olp audio differential line out amplifier for left and right channels. this outputs can drive up to 1k ? resistive load. can be used as single ended output. j3 ao 2olp audio differential line out amplifier for left and right channels. this outputs can drive up to 1k ? resistive load. can be used as single ended output. j4 ao 2hpl audio single ended headphones amplifier outputs for left and right channels. the outputs can drive 50nf (with series resistor) or directly an earpiece transductor of 16 ? . j5 ao 1vcmhp common mode voltage headphones output. the negative pins of headphones left and right speakers can be connected to this pin to avoid decoupling capacitors. j6 ai 1capear a capacitor can be connected between this node and ground j7 ao 1earn analog differential loudspeaker amplifier output for left channel or right channel or the sum of both. this output can drive 50nf (with series resistor) or directly an earpiece transductor from 8 ? to 32 ? .; it can deliver from 500mw to 125mw. j8 p vccls power supply pin for the mono differential output driver. operating range: from v cca to 5.5v j9 ao 2orp audio differential line out amplifier for left and right channels. this outputs can drive up to 1k ? resistive load. can be used as single ended output. j10 ao 1orn audio differential line out amplifier for left and right channels. this outputs can drive up to 1k ? resistive load. can be used as single ended output. j11 ai 1lineinr left and right channel single ended pins for line input k1 p gndcm ground pin for analog reference. gndcm can be connected to gnda k2 p vccp power supply pins for the left and right output drivers (headphones and line-out). operating range: from v cca to 3.3v k3 ao 1hpl audio single ended headphones amplifier outputs for left and right channels. the outputs can drive 50nf (with series resistor) or directly an earpiece transductor of 16 ? . k4 ao 2vcmhps vcmhps (sense) pin must be connected on the application board to vcmhp pin. the connection must be as close as possible to the pins. k5 p vccls power supply pin for the mono differential output driver. operating range: from v cca to 5.5v k6 p gndp ground pin for the left, right and mono-differential output drivers. gndp and gnda must be connected together. k7 p gndp ground pin for the left, right and mono-differential output drivers. gndp and gnda must be connected together. table 1. STW5098 pin description position type pin name description pinout STW5098 14/85 k8 ao 1earns earps, earns (sense) pins must be connected on the application board to earp, earn pins respectively. the connection must be as close as possible to the pins. k9 p vccls power supply pins for the mono differential output driver. operating range: from v cca to 5.5v k10 ao 1orp audio differential line out amplifier for left and right channels. this outputs can drive up to 1k ? resistive load. can be used as single ended output. k11 p gndp ground pin for the left, right and mono-differential output drivers. gndp and gnda must be connected together. l1 p vccp power supply pin for the left and right output drivers (headphones and line-out). operating range: from v cca to 3.3v l2 p gndp ground pin for the left, right and mono-differential output drivers. gndp and gnda must be connected together. l3 ao 1vcmhps vcmhps (sense) pin must be connected on the application board to vcmhp pin. the connection must be as close as possible to the pins. l4 ao 2vcmhp common mode voltage headphones output. the negative pins of headphones left and right speakers can be connected to this pin to avoid decoupling capacitors. l5 ao 2lsps lsps, lsns (sense) pins must be connected on the application board to lsp, lsn pins respectively. the connection must be as close as possible to the pins. l6 ao 2lsp analog differential loudspeaker amplifier output for left channel or right channel or the sum of both. this output can drive 50nf (with series resistor) or directly an earpiece transductor of 8 ? .; it can deliver up to 500mw. l7 ai 2capls a capacitor can be connected between this node and ground l8 ao 2lsn analog differential loudspeaker amplifier output for left channel or right channel or the sum of both. this output can drive 50nf (with series resistor) or directly an earpiece transductor of 8 ? . can deliver up to 500mw. l9 ao 2lsns lsps, lsns (sense) pins must be connected on the application board to lsp, lsn pins respectively. the connection must be as close as possible to the pins. l10 p vccp power supply pin for the left and right output drivers (headphones and line-out). operating range: from v cca to 3.3v l11 ao 2hpr audio single ended headphones amplifier outputs for left and right channels. the outputs can drive 50nf (with series resistor) or directly an earpiece transductor of 16 ? . table 1. STW5098 pin description position type pin name description STW5098 pinout 15/85 type definitions ai - analog input ao - analog output aio - analog input output di - digital input do - digital output dio - digital input output diod - digital input output open drain p - power supply or ground block diagram STW5098 16/85 3 block diagram figure 2. STW5098 block diagram transient suppr. filter transient suppr. filter transient suppr. filter left lineout -40:0 db step 2 -40:0 db step 2 right driver log: -18:0 db step 3 right lineout l (l+r)/2 r stereo diff. stereo sing.e. stereo sing.e. stereo diff. stereo sing.e. comm. mode left driver cm driver voltage reference -20 : +18 db step 2 -24 : 6 db step 2 mono driver miclo1 lssel1 mixlin1 mixmic1 admic1 adlin1 1caplinein 1capmic 1lineinl 1lineinr 1aux3r 1aux3l aux2nr 1aux2pr 1aux2nl 1aux2pl 1aux1r 1aux1l 1micrn 1micrp 1micln 1miclp 1mbias 1vcmhp 1vcmhps 1olp 1oln 1hpl 1earps 1earp 1capear 1earn 1earns 1hpr 1orp 1orn mic. bias linein aux1 aux2 aux3 mute lin l-r amps linsel1 linlg1 linrg1 stereo path 2.1v reference agc (from dsp) agc (from dsp) rl lsg1 hplg1 hprg1 0 39 db step 1.5 mic aux1 aux2 aux3 mute mic l-r preamps micsel1 miclg1 micrg1 -12 0 db step 1.5 micla1 micra1 l r l r transient suppr. filter transient suppr. filter transient suppr. filter left lineout -40:0 db step 2 -40:0 db step 2 right driver log: -18:0 db step 3 right lineout l (l+r)/2 r stereo diff. stereo sing.e. stereo sing.e. stereo diff. stereo sing.e. comm. mode left driver cm driver voltage reference -20 : +18 db step 2 -24 : 6 db step 2 mono driver miclo2 lssel2 mixlin2 mixmic2 admic2 adlin2 2caplinein 2capmic 2lineinl 2lineinr 2aux3r 2aux3l 2aux2nr 2aux2pr 2aux2nl 2aux2pl 2aux1r 2aux1l 2micrn 2micrp 2micln 2miclp 2mbias 2vcmhp 2vcmhps 2olp 2oln 2hpl 2lsps 2lsp 2capls 2lsn 2lsns 2hpr 2orp 2orn mic. bias linein aux1 aux2 aux3 mute lin l-r amps linsel2 linlg2 linrg2 stereo path 2.1v reference agc (from dsp) agc (from dsp) r l lsg2 hplg2 hprg2 0 39 db step 1.5 mic aux1 aux2 aux3 mute mic l-r preamps micsel2 miclg2 micrg2 -12 0 db step 1.5 micla2 micra2 l r l r mck1 da sample rate converter ck gen/ master mode digital da-pll pll audio ad-i/f stereo dac 1ad_sync 1ad_ck 1ad_data 1ad_ock amck 1da_ock 1da_sync 1da_ck 1da_data dsp1 ad to da mixing gain agc (mic&lin) dachsw admono damono (sidetone) dac digital gain adc digital gain dyn.comp. bass treble (audio only) da to ad mixing gain (audio only) adchsw filter audio/voice filter audio/voice ? modulator ? adc audio da-i/f da_sync1 ck gen/ master mode mck2 ck gen/ master mode pll audio ad-i/f 2ad_sync 2ad_ck 2ad_data 2ad_ock amck 2da_ock 2da_sync 2da_ck 2da_data dsp2 ad to da mixing gain agc (mic&lin) dachsw admono damono (sidetone) dac digital gain adc digital gain dyn.comp. bass treble (audio only) da to ad mixing gain (audio only) adchsw filter audio/voice filter audio/voice audio da-i/f ck gen/ master mode bandgap control logic power-on reset registers control i/f headset detection vccio gnd vcc gndcm gndp vccls vccp gnda currentbias STW5098 irq gen 2cmod 2as/csb 1sclk 2sda/sdin 1hdet oscillator stereo adc dac mixdac1 analog filter ad sample rate converter digital ad-pll ad_sync1 stereo dac ? adc stereo adc ad sample rate converter digital ad-pll ad_sync2 da sample rate converter digital da-pll ? modulator da_sync2 dac mixdac2 analog filter 1irq 2hdet amck vcca 1sda/sdin 2sclk 1cmod 1as/csb 2irq STW5098 functional description 17/85 4 functional description 4.1 naming convention the STW5098 is composed of two identical entities, with their respective set of control registers. regarding the pin labelling, a pin name preceded by 1 refers to entity 1 and a pin name preceded by 2 refers to entity 2 (ie.g. 1sclk, 2sclk). in the following sections, no distinction is made between the two entities when it is not relevant. consequently, the 1 and 2 prefixes for entities 1 and 2 respectively are omitted. the same naming convention applies to the control registers (crxxx). 4.2 power supply STW5098 can have different supply voltages for different blocks, to optimize performance, power consumption and connectivity. see section 9.2 on page 59 for voltage definition. the correct sequence to apply supply voltage is to set first (and unset last) the digital i/o supply (v ccio ). the other supply voltages can be set in any order and can be disconnected individually, if needed. disconnection does not cause any harm to the device and no extra current is pulled from any supply during this operation. moreover if a voltage conflict is detected, like v cca < v cc (not allowed), simply all blocks connected to v cca are set to power down and no extra current is pulled from supply. when v ccio is set and v cc (digital supply) is not set, all the digital output pins are in high impedance state, while the digital inputs are disconnected to avoid power consumption for any input voltage value between gnd and v ccio . before v cc is disconnected the device has to be reset (swres bit in cr30). when the analog supply (v cca ) is set and v cc is not set, all the analog inputs are in high impedance state. the two sets of control registers are powered by vcc pins (digital supply) so if these pins are disconnected all the information stored in control registers is lost. when the digital supply voltage is set, a power-on-reset (por) circuit sets all the registers content to the default value and then generates irq signals writing 1 in bits pormsk end porev in cr31 and cr32 respectively for both entities. all supplies must be on during operation. functional description STW5098 18/85 4.3 device programming STW5098 can be programmed by writing control registers with spi or i 2 c compatible control interface (both slave). the interface is always active, there is no need to have the master clock running to program the device registers. the control interfaces of each entity can be operated independently either in spi or i2c modes. the choice between the two interfaces for each entity is done via their input pins 1cmod and 2cmod (cmod): 1. cmod connected to gnd: i 2 c compatible mode selected the device address is selected with as pin: when this mode is selected control registers are accessed through pins: sclk (clock) sda (serial data out/in, open drain) 2. cmod connected to v ccio : spi compatible mode selected when this mode is selected control registers are accessed through: as/csb (chip select, active low) sclk (clock) sdin (serial data in) ad_ock or da_ock or irq (serial data out, if selected) device programming: i 2 c . the i 2 c control interface timing is shown in section 6.1 on page 50 . the interface has an internal counter that keeps the current address of the control register to be read or written. at each write access of the interface the address counter is loaded with the data of the register address field. the value in the address counter is increased after each data byte read or write. it is possible to access the interface in 2 modes: single-byte mode in which the address and data of a single register are specified, and multi-byte mode in which the address of the first register to be written or read is specified and all the following bytes exchanged are the data of successive registers starting from the one specified (in multi-byte mode the internal address counter restart from register 0 after the last register 36). using the multi-byte mode it is possible to write or read all the registers with a single access to the device on the i 2 c bus. this applies to both entities of the device. device programming: spi. the spi control interface timing is shown in section section 6.2 on page 51 . bits spiosel (spi output select) in cr33 control the out pin selection for serial data out (none, ad_ock, da_ock or irq), while bit spiohiz=1 in cr33 selects the high impedance state of serial data out pin when idle. the first bit sent on sdin, after as/csb falling edge, sets the interface for writing (sdin=1) or reading (sdin=0), then a 7-bit control register address follows. if the interface is set for writing then the last 8 bits on sdin are written in the control register. if the interface is set for reading then after the 7 bit address STW5098 sends out 8 bits data on the pin selected with bits spiosel in cr33, while bits present at sdin pin are ignored. if spiosel=00 (no out pin selected) the reading access on spi interface can still be useful to clear the irq event bits in cr32. as/csb connected to gnd: chip address 001101 0 1(35hex) for reading, 001101 0 0 (34hex) for writing as/csb connected to v ccio : chip address 001101 1 1(37hex) for reading, 001101 1 0 (36hex) for writing STW5098 functional description 19/85 4.4 power up STW5098 internal blocks can individually be switched on and off according to the user needs. a general power-up bit is present at bit 7 of cr0. the output drivers should always be powered up after the general power up. see the following drawing to select the needed block for the desired function. a fast-settling function is activated to quickly charge external capacitors when the device is switched on (capls, caplinein and capmic). figure 3. power up block diagram: example shown for one entity 4.5 master clock master clock is applied to both entities. the master clock pin (amck) accepts any frequency from 4 mhz to 32 mhz. the 4-32 mhz range is divided in sub-ranges that have to be programmed in bits ckrange in cr30. the jitter and spectral properties of this clock have a direct impact on the dac and adc performance because it is used to directly or by integer division drive the continuous-time to sampled-time interfaces. powerup enana STW5098 enmixl enmixl enhpvcm enhpl enls enhpr enmicr enmicl enlinr enlinl enosc enadcr enadcl endacr endacl audio i/f enlol enlor enhsd enpll damast endaock admast enadock mbias enamck endackgen enadckgen enosc =1 enosc =0 functional description STW5098 20/85 note that amck clock does not need to have any relation to any other digital or analog input or output. amck can be either a square wave or a sinewave, bit amcksin in cr30 selects the proper input mode. when a sinewave is used as input, amck pin must be decoupled with a capacitor. specification for sinusoid input can be found in section 10.2 on page 62 . the amck clock is not needed when only analog functions are used. for this purpose an internal oscillator with no external components can be used to operate the device (see section 4.14 on page 25 ). 4.6 data rates STW5098 supports any data rate in 2 ranges: 8 khz to 48 khz and 88 khz to 96 khz. the range is selected with bits da96k and ad96k in cr29 for ad and da paths respectively. note: when ad96k=1 it is required to have da96k=1. the rates are fully independent in a/d and d/a paths. moreover the rates do not have to be specified to the device and they can change on the fly, within one range, while data is flowing. the 2 audio data interfaces (for a/d and d/a) can independently operate in master or slave modes. 4.7 clock generators and master mode function STW5098 provides 4 internal clock generators that can drive, if needed, the audio interfaces (master mode), and/or two independent master clocks. the amck clock input frequency is internally raised via a pll on each entity to obtain a clock (mck) in the range 32 mhz to 48 mhz. the ratio mck/amck is defined in cr30 (see mckcoeff in section 4.7 on page 20 ). mck is used to obtain, by fractional division, the oversampled clock (ock), word clock (sync) and bit clock (ck), that will therefore have edges aligned with mck (the ock period can have jitter of 1 mck period). the frequency of ock, sync and ck is set with daockf in cr21/20 for da interface, and adockf in cr24/23 for ad interface. the ratio between ock and sync clocks is selected with bit daock512 in cr22 for da interface and bit adock512 in cr25 for ad interface. the ratio between ck and sync clocks depends on the selected interface format (see audio digital interfaces paragraph below). note that spi format can only be slave. the adock and daock output clocks are activated by bits enadock and endaock respectively, while master mode generation is activated with two bits: first admast (damast) sets adsync and adck (dasync and dack) pins as outputs, then admastgen (damastgen) generates the sync and ck clocks. the logical value at sync and ck pins before data generation depends on the interface selected format. see description of cr20 to cr25 for further details. STW5098 functional description 21/85 4.8 audio digital interfaces four separate audio data interfaces are provided for ad and da paths to have maximum flexibility in communicating with other devices. the 4 interfaces can have different rates and can work in different formats and modes (i.e an ad interface can be 8 khz pcm slave while a da is 44.1 khz i 2 s master). the pins used by the interfaces are: ad_sync, ad_ck and ad_data for ad paths word clock, bit clock and data, respectively, and da_sync, da_ck and da_data for da paths word clock, bit clock and data, respectively. data is exchanged with msb first and left channel data first in all formats. data word-length is selected with bits dawl in cr26 and adwl in cr27. ad_data pin, outside the selected time slot, is in the impedance condition selected by bit adhiz in cr28 in all data formats except right aligned format. in the following paragraphs sync, ck and data will be used when the distinction between ad and da is not relevant. when master mode is selected (bits damast and admast in cr22 and cr25 respectively) the sync and ck clocks are generated internally. in addition, an oversampled clock can be generated for each interface (ad_ock and da_ock). the clock is available in slave mode also, if needed. the ad and da interfaces can also be used as a single bidirectional interface when they are configured with the same format (delayed, dsp, etc.) and ad_sync is connected to da_sync and da_ck to ad_ck. master mode is still available selecting admast or damast (not both). the interfaces features are controlled with control registers cr26, cr27 and cr28. supported operating formats: delayed format (i 2 s compatible) (daform or adform =000): the audio interface is i 2 s compatible ( figure 9 on page 54 ). the number of ck periods within one sync period is not relevant, as long as enough ck periods are used to transfer the data and the maximum frequency limit specified for bit clock is not exceeded. ck can be either a continuous clock or a sequence of bursts. in master mode there are 32 ck periods per sync period (that means 16 ck periods per channel) when the word length is 16 bit, while there are 64 ck periods per sync period (or 32 ck periods per channel) when word length is 18bit or higher. bits adsyncp, dasyncp and adckp, dackp affect the interface format inverting the polarity of sync and ck pins respectively. left aligned format (daform or adform =001): this format is equivalent to delayed format without the 1 bit clock delay at the beginning of each frame ( figure 9 on page 54 ). right aligned format (daform or adform =010): this format is equivalent to delayed format, except that the audio data is right aligned and that the number of ck periods is fixed to 64 for each sync period ( figure 9 on page 54 ). dsp format (daform or adform =011) in this format the audio interface starting from a frame sync pulse on sync receives (da) or sends (ad) the left and right data one after the other ( figure 10 on page 55 ). the number of ck periods within one sync period is not relevant, as long as enough ck periods are used to transfer the data and the maximum frequency limit specified for bit clock is not exceeded. ck can be either a continuous clock or a sequence of bursts. in master mode there are 32 ck periods per sync period when the word length is 16 bit, while there are 64 ck periods per sync period when word length is 18bit or higher. bit ckp (adckp and dackp) functional description STW5098 22/85 affects the interface format inverting the polarity of ck pin. bit syncp (adsyncp and dasyncp) switches between delayed (syncp=0) and non delayed (syncp=1) formats. dsp format is suited to interface with a multi-channel serial port. spi format (daform or adform =100) in this format left and right data is received with separate data burst. every burst is identified with a low level on sync signal ( figure 10 on page 55 ). there is no timing difference between the left and right data burst: the two channels are identified by the startup order: the first burst after ad path or da path power-up identifies the left channel data, the second one is the right channel data, then left and right data repeat one after the other. ck must have 16 periods per channel in case of 16 bit data word and 32 periods per channel in case of 18 bit to 32 bit data word. the spi interface can be configured as a single-channel (mono) interface with bit spim (adspim and daspim). the mono interface always exchanges the left channel sample. spi-format can only be slave: if master mode is selected the ck and sync pins are set to 0. bit ckp (adckp and dackp) affects the interface format inverting the polarity of ck pin. pcm format (daform or adform =111): this format is monophonic, as it can only receive (da) and transmit (ad) single channel data ( figure 10 on page 55 ). it is mainly used when voice filters are selected. if audio filters are used then the same sample is sent from da-pcm interface to both channel of da path, and the left channel sample from ad path is sent to ad-pcm interface. if in the ad path the right channel has to be sent to the pcm interface then the following must be set: adrtol=1 (cr27) and enadcr=0 (cr1). in master mode the number of ck periods per sync period is between 16 and 512 (see dapcmf in cr22 and adpcmf in cr25 section 4.7 on page 20 for details). bit ckp (adckp and dackp) affects the interface format inverting the polarity of ck pin. bit syncp (adsyncp and dasyncp) switches between delayed (syncp=0) and non delayed (syncp=1) formats. 4.9 analog inputs each entity of the STW5098 has a stereo microphone preamplifier and a stereo line in amplifier, with inputs selectable among 5: mic (for microphone preamplifiers only), linein (for line in amplifiers only) and 3 different aux inputs (for microphone and line in amplifiers). the aux inputs can be used simultaneously for line in amplifiers and microphone preamplifiers. the following description is for one entity, it is similar for the other entity. microphone preamplifier: it has a very low noise input, specifically designed for low amplitude signals. for this reason the preamplifier has a high input gain (up to 39 db) keeping a constant 50 k ? input impedance for the whole gain range. however it can also be used as line in preamplifier because it can accept a high dynamic input signal (up to 4 v pp ). there are two separate gain and attenuation stages in order to improve the s/n ratio when the preamplifier output range is below full scale (volume control).the gain and attenuation controls are separate for left and right channel (cr3 and cr4 respectively). the preamplifier input is selected with bits micsel in cr18, and it is disconnected when micmute=1. if a single ended input is selected then the preamplifier uses the selected pin as the positive input and connects the negative input (for both left and right channels) to capmic pin, which has to be connected through a capacitor to a low noise ground (typically the same reference ground of the input). STW5098 functional description 23/85 each stereo microphone preamplifier is powered up with bits enmicl and enmicr in cr1. line in amplifier: each line in amplifier is designed for high level input signal. the input gain is in the range -20 db up to 18 db. the line in amplifier input is selected with bits linsel in cr18, and it is disconnected when linmute=1. if a single ended input is selected then the amplifier uses the selected pin as the positive input and connects the negative input (for both left and right channels) to caplinein pin, which has to be connected through a capacitor to a low noise ground (typically the same reference ground of the input). the stereo line in amplifier is powered up with bits enlinl and enlinr in cr1. 4.10 analog output drivers each entity of the STW5098 provides 3 different analog signal outputs and 1 common mode reference output. the description here below is for one entity. v ccp and v ccl are common for both entities. line out drivers: it is a stereo differential output, it can be used as single-ended output just by using the positive or negative pin. it can drive 1 k ? resistive load. the load can be connected between the positive and negative pins or between one pin and ground through a decoupling capacitor. the output gain is regulated with log bits in cr7, in the range 0 to -18 db, simultaneously for left and right channels. when used as a single ended output the effective gain is 6 db lower. it is muted with bit mutelo in cr19. the input signal of this stereo output can come from the analog mixer or directly from mic preamplifiers. the output common mode voltage level is controlled with bits vcml in cr19. the supply voltage of line out drivers is v ccp . the line out drivers are powered up with bits enlol and enlor in cr1. the output pins are in high impedance state with a 180k ? pull-down resistor when the line out drivers are powered down. headphones drivers: it is a stereo single ended output. it can drive 16 ohm resistive load and deliver up to 40 mw. the output gain is regulated with hplg and hprg bits in cr8 and cr9 respectively, with a range of -40 to 6 db. it is muted with bit mutehp in cr19. the input signal of this stereo output comes from the analog mixer.the output common mode voltage is controlled with bits vcml in cr19. the supply voltage of headphones drivers is v ccp . the headphones drivers are powered up with bits enhpl and enhpr in cr2.the output pins are in high impedance state when the headphones drivers are powered down. common mode voltage driver: it is a single ended output with output voltage value selectable with bits vcml in cr19, from 1.2 v to 1.65 v in steps of 150 mv. the output voltage should be set to the value closest to v ccp /2 to optimize output drivers performance. the common mode voltage driver is designed to be connected to the common pin of stereo headphones, so that decoupling capacitors are not needed at hpl and hpr outputs. the supply voltage of the common mode voltage driver is v ccp . the common mode voltage driver is powered up with bit enhpvcm in cr2.the output pin is in high impedance state when the common mode voltage driver is powered down. functional description STW5098 24/85 loudspeaker driver (one entity only): it is a monophonic differential output. it can drive 8 ? resistive load and deliver up to 500 mw to the load. the output gain is regulated with lsg bits in cr7, in the range -24 to +6 db. the input signal of the loudspeaker driver comes from the analog mixers: bits lssel in cr29 select left channel, right channel, (l+r)/2 (mono) or mute. the output common mode voltage is obtained with an internal voltage divider from v ccls and it is connected to capls pin. the supply voltage of the loudspeaker driver is v ccls . the loudspeaker driver is powered up with bit enls in cr2.the output pin is in high impedance state when the loudspeaker driver is powered down. note: 1 together with the ls driver, only a second power output is allowed among: ear (1earp - 1earn) headphones 1 (1hpl and 1hpr) headphones 2 (2hpl and 2hpr) earphone driver (one entity only): it is a monophonic differential output. it can drive 32 ? resistive load and deliver up to 125 mw to the load. the output gain is regulated with earg bits in cr7, in the range -24 to +6 db. the input signal of the loudspeaker driver comes from the analog mixers: bits earsel in cr29 select left channel, right channel, (l+r)/2 (mono) or mute. the output common mode voltage is obtained with an internal voltage divider from v ccls and it is connected to capear pin. the supply voltage of the loudspeaker driver is v ccls . the loudspeaker driver is powered up with bit enear in cr2.the output pin is in high impedance state when the loudspeaker driver is powered down. note: note on direct connection of v ccls to the battery: the voltage of batteries of handheld devices during charging is usually below 5.5 v, making v ccls supply pin suitable for a direct connection to the battery. in this case if STW5098 is delivering the maximum power to the load and the ambient temperature is above 70 c then the simultaneous charging of the battery can overheat the device. a basic protection scheme is implemented in STW5098 (activated with bit lslim in cr19): it limits the maximum gain of the loudspeaker to -6 db when v ccls is above 4.2 v, and it removes the limit for v ccls below 4.0 v. the loudspeaker gain is left unchanged if it is set below -6 db with bits lsg. this event (v ccls > 4.2 v) can generate, if enabled (bit vlsmsk in cr31), an irq signal. 4.11 analog mixers STW5098 can send to the output drivers the sum of stereo audio signals from 3 different sources of each entity: da path (bit mixdac in cr17), microphone preamplifiers (bit mixmic in cr17) and line in amplifiers (bit mixlin in cr17). the analog mixers do not have a gain control on the inputs, therefore the user should reduce the levels of the input signals within the analog signal range. the stereo analog mixers are powered up with bits enmixl and enmixr in cr2. 4.12 ad paths in each entity the ad path converts audio signals from microphone preamplifiers (selected with bit admic in cr17) and line in amplifiers (bit adlin in cr17) inputs to digital domain. if both inputs are selected then the sum of the two is converted. after ad conversion the audio data is resampled with a sample rate converter and then processed with the internal dsp. two different filters are selectable in the dsp (bit advoice in cr29): stereo audio STW5098 functional description 25/85 filter, with dc offset removal and fir image filtering; and a standard mono voice-channel filter (uses left channel input and feeds both channel output). the ad path includes a digital gain control (adclg, adcrg in cr12 and cr13 respectively) in the range -57 to +8 db. the maximum gain from mic preamplifier to ad interface is then 47 db. when audio filter is selected in both ad and da paths then da audio data can be summed to ad data and sent to the ad audio interface (see da2adg in cr15). left and right channels can be independently switched on and off to save power, if needed (bits enadcl and enadcr in cr1) 4.13 da paths in each entity the da path converts digital data from the digital audio interface to analog domain and feeds it to the analog mixer. incoming audio data is processed with a dsp where different filters are selectable (bit davoice in cr29): audio filter, stereo, with fir image filtering, bass and treble controls (bits bass and treble in cr14), de-emphasis filter; and a standard voice channel filter, mono (uses left channel input and feeds both channel output). a dynamic compression function is available for both audio and voice filters (bit dync in cr14). the da path includes a digital gain control (daclg, dacrg in cr10 and cr11 respectively) in the range -65 to 0 db. ad to da mixing (sidetone) can be enabled: see cr16 for details. left and right channel can be independently switched on and off to save power, if needed (bits endacl and endacr in cr1). 4.14 analog - only operations each entity from the STW5098 can operate without amck master clock if analog-only functions are used. it is possible to mix microphone and line in preamplifiers signals and listen through headphones, loudspeaker or send them to line-out. the analog-only operation is enabled with bit enosc in cr0. when enosc=1 the ad and da paths cannot be used. in analog mode, each of the two entities can handle two different stereo audio signals, so it can be used as a front end for an external voice codec that does not include microphone preamplifiers and power drivers: mic signal is sent through microphone preamplifiers directly to line out drivers (transmit path), while receive signal is sent through line in amplifiers to the selected power drivers. 4.15 automatic gain control (agc) STW5098 provides a digital automatic gain control in ad path for each entity. the circuit can control the input gain at mic preamplifier, line in amplifier or both (bits enagcmic and enagclin in cr35). when one input is selected, the center gain value used for the input is fixed with bits miclg, micrg, linlg and linrg in cr3 to cr6 (like in normal operation), then the agc circuit adds to all the gains a value in the range -10.5 db to +10.5 db (or, extended with bit agcrange in cr35, -21 db to 21 db), in order to obtain an average level at the digital interface output in the range -6 db to -30 db (selected with bits agclev in cr35). the agc added gain acts directly in the input gain, to avoid input saturation and improve s/n ratio, so it cannot exceed the input gain range. when mic and line-in inputs are selected simultaneously the control is performed on the sum of the two, preserving the balance fixed with input gains. different values for attack and decay constants can be selected, depending on the kind of signal the agc has to control (i.e. voice, music). the functional description STW5098 26/85 attack and decay time constants are related to the ad data rate (see bits agcatt and agcdel in cr34). 4.16 interrupt request: irq pins on each entity of the STW5098, the interrupt request feature can signal to a control device the occurrence of particular events on each entity. two control registers are used to choose the behavior of irq pin: the first is a status/event register (cr32), where bits can represent the status of an internal function (i.e. a voltage is above or below a threshold) or an event (i.e. a voltage changed crossing a threshold); the second is a mask register (cr31) where if a bit in the mask is set to 1 then the corresponding bit in the status/event register can affect irq pin status. on each entity, the irq pin is always active low. at v cc power up an interrupt request is generated by the power-on-reset circuit that sets to 1 bits pormsk in cr31 and porev in cr32. after this event the pormsk bit should be cleared by the user and bit irqcmos in cr33 should be set according to the application (open drain or cmos). when an irq event occurs and spi control interface is selected with no serial output pin it is still possible to identify the event (and relative status) that generated the interrupt request. this can be done by setting the irq mask/enable bits (in cr31) one at the time (with successive writings) and reading the irq pin status. a simple example of this is the headset plug-in detection: at first we set bit hsdetmsk=1 in cr31 (with all the other bits set to 0). if there is an interrupt request then we set hsdetmsk=0 and hsdeten=1, so we can read the hsdet status at irq pin. then we read cr32 to clear its content (even if no data is sent out). 4.17 headset plug-in and push-button detection each entity of the STW5098 can detect the plug-in of a microphone connector and the press/release event of a call/answer push-button. an application example can be found below, while specifications can be found in section 10.4 on page 64 . figure 4. plug-in and push-button detection application note call/answer button 10 f 1.5k ? vcca 3k ? 200nf aux1l aux1r capmic hdet 200nf stw5095 generic connector from driver STW5098 functional description 27/85 4.18 microphone biasing circuits the microphone biasing circuits can drive mono or stereo microphones and can switch them off when not needed in order to save the current used by the microphone biasing network on each entity. two bits control the behavior of the microphone bias circuit: mbias in cr17 enables the circuit (fixed voltage at mbias pin), while bit mbiaspd in cr17 affects the behavior of mbias pin when the function is not enabled. in particular when mbiaspd=1 the mbias pin is pulled down, otherwise it is left in tristate mode. the specification for the microphone biasing circuits can be found in section 10.6 on page 64 . control registers STW5098 28/85 5 control registers 5.1 summary table 2. control register summary cr# (hex) descriptiond7d6d5 d4 d3d2d1d0def. cr0 (00h) supply & power control #1 power up enana enamck enosc enpll enhsd a24v d12v 0000 0000 cr1 (01h) power control #2 enadcl enadcr endacl endacr enmicl enmicr enlinl enlinr 0000 0000 cr2 (02h) power control #3 enlol enlor enhpl enhpr enhpvc m 1enear 2enls enmixl enmixr 0000 0000 cr3 (03h) mic gain left micla(2:0) miclg(4:0) 0000 0000 cr4 (04h) mic gain right micra(2:0) micrg(4:0) 0000 0000 cr5 (05h) line in gain left x x x linlg(4:0) 0000 1001 cr6 (06h) line in gain right x x x linrg(4:0) 0000 1001 cr7 (07h) lo gain & ls gain xlog(2:0) 1earg(3:0) 2lsg(3:0) 0000 0011 cr8 (08h) hpl gain xx x hplg(4:0) 0000 0011 cr9 (09h) hpr gain xx x hprg(4:0) 0000 0011 cr10 (0ah) dac digital gain left x x daclg(5:0) 0000 0000 cr11 (0bh) dac digital gain right x x dacrg(5:0) 0000 0000 cr12 (0ch) adc digital gain left x x adclg(5:0) 0000 1000 cr13 (0dh) adc digital gain right x x adcrg(5:0) 0000 1000 cr14 (0eh) bass/treble/de- emphasis dync treble(2:0) bass(3:0) 0000 0000 cr15 (0fh) da to ad mixing gain x x x da2adg(4:0) 0000 0000 cr16 (10h) ad to da mix/sidetone gain xx ad2dag(5:0) 0000 0000 cr17 (11h) mixer switches & mic bias mbias m biaspd admic adlin mixmic mixlin mixdac miclo 0000 0000 STW5098 control registers 29/85 cr18 (12h) input switches x in2vcm linmute linsel(1:0) micmute micsel(1:0) 0010 0100 cr19 (13h) drivers control vcml(1:0) x mutelo mutehp 1earlim 2lslim 1earsel(1:0) 2lssel(1:0) 0101 1000 cr20 (14h) daock frequency lsb daockf(7:0) 0000 0000 cr21 (15h) daock frequency msb daockf(15:8) 0000 0000 cr22 (16h) da clock generator control xxdamast da mastgen end aock dao ck512 dapcmf(1:0) 0000 0000 cr23 (17h) adock frequency lsb adockf(7:0) 0000 0000 cr24 (18h) adock frequency msb adockf(15:8) 0000 0000 cr25 (19h) ad clock generator control xxadmast ad mastgen ena dock ado ck512 adpcmf(1:0) 0000 0000 cr26 (1ah) dac data if control x daform(2:0) daspim dawl(2:0) 0000 0000 cr27 (1bh) adc data if control adrtol adform2:0) adspim adwl(2:0) 0000 0000 cr28 (1ch) dac&adc data if control amc kinv dackp dasyncp damono adckp ad syncp admono adhiz 0000 0000 cr29 (1dh) digital filters control x davoice da96k rxnh advoice ad96k adnh txnh 0000 0000 cr30 (1eh) soft reset & amck range swres x x x amcksin ckrange(2:0) 0000 0000 cr31 (1fh) interrupt mask vlshen push ben hsdeten vlshmsk push bmsk hsdet msk ovfmsk pormsk 0000 0000 cr32 (20h) interrupt status vlsh pushb hsdet vlshev pushbev hsdetev ovfev porev 0000 0000 cr33 (21h) misc. control x x spiohiz spiosel(1:0) irqcmos ovfda ovfad 0000 0000 cr34 (22h) agc attack/decay coeff. agcatt(3:0) agcdec(3:0) 0000 0000 cr35 (23h) agc control x ena gclin enag cmic agc range agclev(3:0) 0000 0000 cr36 (24h) reserved xxx x xxxx 0000 0000 note: x reserved, write zero table 2. control register summary cr# (hex) descriptiond7d6d5 d4 d3d2d1d0def. control registers STW5098 30/85 caution: in the following section 5: control registers , reference to each entity is omitted. each entity of the STW5098 has the same register set. 5.2 supply and power control cr# (hex) descriptiond7d6d5d4d3d2d1d0def. cr0 (00h) supply & power control #1 power up enana enamck enosc enpll enhsd a24v d12v 0000 0000 cr1 (01h) power control #2 enadcl enadcr endacl endacr enmicl enmicr enlinl enlinr 0000 0000 cr2 (02h) power control #3 enlol enlor enhpl enhpr enh pvcm enls enmixl enmixr 0000 0000 table 3. cr0 description bits name val. cr0 description def. 7powerup 1 0 all the enabled analog and digital blocks are in power up all the device is in power down 0 6 enana 1 0 the analog blocks can be enabled all the analog blocks are in power down 0 5enamck 1 0 amck clock input pin is enabled amck clock input pin is disabled 0 4enosc 1 0 the internal oscillator is enabled. the analog blocks use oscillator clock the internal oscillator is in power down 0 3enpll 1 0 the pll is enabled the pll is in power down 0 2 enhsd 1 0 the headset plug-in detector is enabled the headset plug-in detector is disabled 0 1a24v 1 0 analog supply pins voltage range is 2.4v control registers STW5098 32/85 5.3 gains cr# (hex) descriptiond7d6d5d4d3d2d1d0def. cr3 (03h) mic gain left micla(2:0) miclg(4:0) 0000 0000 cr4 (04h) mic gain right micra(2:0) micrg(4:0) 0000 0000 cr5 (05h) line in gain left xxx linlg(4:0) 0000 1001 cr6 (06h) line in gain right x x x linrg(4:0) 0000 1001 cr7 (07h) lo gain & ls gain x log(2:0) lsg(3:0) 0000 0011 cr8 (08h) hpl gain xxx hplg(4:0) 0000 0011 cr9 (09h) hpr gain xxx hprg(4:0) 0000 0011 cr10 (0ah) dac digital gain left x x daclg(5:0) 0000 0000 cr11 (0bh) dac digital gain right x x dacrg(5:0) 0000 0000 cr12 (0ch) adc digital gain left x x adclg(5:0) 0000 1000 cr13 (0dh) adc digital gain right x x adcrg(5:0) 0000 1000 table 6. cr3 and cr4 description bits name cr3 name cr4 value cr3 and cr4 description def. 7-5 micla(2:0) micra(2:0) 000 001 010 ... 110 111 left (cr3) and right (cr4) channels microphone attenuation 0.0 db gain (default) -1.5 db gain -3.0 db gain ...step 1.5 db -9.0 db gain -12.0 db gain 000 4-0 miclg(4:0) micrg(4:0) 00000 00001 00010 ... 11010 left (cr3) and right (cr4) channels microphone gain 0.0 db gain (default) 1.5 db gain 3.0 db gain ...step 1.5 db 39.0 db gain 00000 STW5098 control registers 33/85 table 7. cr5 and cr6 description bits name cr5 name cr6 value cr5 and cr6 description def. 4-0 linlg(4:0) linrg(4:0) 00000 00001 00010 ... 01001 ... 10011 left (cr5) and right (cr6) channels line in gain 18.0 db gain 16.0 db gain 14.0 db gain ...step 2.0 db 0.0 db gain (default) ...step 2.0 db -20.0 db gain 01001 table 8. cr7 description bits name value cr7 description def. 6-4 log(2:0) 000 001 010 ... 110 left and right channel line out drivers gain gain to differential output equivalent single-ended gain 18.0 db gain (default) -24.0 db gain (default) -15.0 db gain -21.0 db gain -12.0 db gain -18.0 db gain ...step 3 db ...step 3 db 00 db gain -6.0 db gain 000 3-0 1earg(3:0) 0000 0001 0010 0011 ... 1111 32 ? earphone gain/ 8 ? loudspeaker gain 6.0 db gain 4.0 db gain 2.0 db gain 0.0 db gain (default) ...step 2.0 db -24.0 db gain 0011 2lsg(3:0) table 9. cr8 and cr9 description bits name cr8 name cr9 value cr8 and cr9 description def. 4-0 hplg(4:0) hprg(4:0) 00000 00001 00010 00011 ... 10100 left (cr8) and right (cr9) channels headphones driver gain 0.0 db gain -2.0 db gain -4.0 db gain -6.0 db gain (default) ...step 2.0 db -40.0 db gain 00011 control registers STW5098 34/85 table 10. cr10 and cr11 description bits name cr10 name cr11 value cr10 and cr11 description def. 5-0 daclg(5:0) dacrg(5:0) 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 left (cr10) and right (cr11) channels dac digital gain 0.0 db gain (default) -1.0 db gain -2.0 db gain -3.0 db gain -4.0 db gain -5.0 db gain -6.0 db gain -7.0 db gain -8.0 db gain -9.0 db gain -10.0 db gain -11.0 db gain -12.0 db gain -13.0 db gain -14.0 db gain -15.0 db gain -16.0 db gain -17.0 db gain -18.0 db gain -20.0 db gain -22.0 db gain -24.0 db gain -26.0 db gain -28.0 db gain -30.0 db gain -32.0 db gain -34.0 db gain -36.0 db gain -38.0 db gain -41.0 db gain -44.0 db gain -47.0 db gain -50.0 db gain -53.0 db gain -56.0 db gain -59.0 db gain -65.0 db gain - db gain 000000 STW5098 control registers 35/85 table 11. cr12 and cr13 description bits name cr12 name cr13 value cr12 and cr13 description def. 5-0 adclg(5:0) acdrg(5:0) 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 left (cr12) and right (cr13) channels adc digital gain 8.0 db gain 7.0 db gain 6.0 db gain 5.0 db gain 4.0 db gain 3.0 db gain 2.0 db gain 1.0 db gain 0.0 db gain (default) -1.0 db gain -2.0 db gain -3.0 db gain -4.0 db gain -5.0 db gain -6.0 db gain -7.0 db gain -8.0 db gain -9.0 db gain -10.0 db gain -11.0 db gain -12.0 db gain -14.0 db gain -16.0 db gain -18.0 db gain -20.0 db gain -22.0 db gain -24.0 db gain -26.0 db gain -28.0 db gain -30.0 db gain -33.0 db gain -36.0 db gain -39.0 db gain -42.0 db gain -45.0 db gain -48.0 db gain -51.0 db gain -57.0 db gain - db gain 001000 control registers STW5098 36/85 5.4 dsp control cr# (hex) descriptiond7d6d5d4d3d2d1d0def. cr14 (0eh) bass/treble/de- emphasis dync treble(2:0) bass(3:0) 0000 0000 cr15 (0fh) da to ad mixing gain xxx da2adg(4:0) 0000 0000 cr16 (10h) ad to da mix/sidetone gain xx ad2dag(5:0) 0000 0000 table 12. cr14 description bits name value cr14 description def. 7dync 1 0 audio dynamic compression in d/a path is enabled audio dynamic compression in d/a path is disabled 0 6-4 treble(2:0) 011 010 001 000 111 110 101 100 treble control in d/a path +6.0 db treble gain +4.0 db treble gain +2.0 db treble gain 0.0 db treble gain -2.0 db treble gain -4.0 db treble gain -6.0 db treble gain de-emphasis filter enabled 000 3-0 bass(3:0) 0101 0100 0011 0010 0001 0000 1111 1110 1101 1100 1011 bass control in d/a path +12.5 db bass gain +10.0 db bass gain +7.5 db bass gain +5.0 db bass gain +2.5 db bass gain 0.0 db bass gain -2.5 db bass gain -5.0 db bass gain -7.5 db bass gain -10.0 db bass gain -12.5 db bass gain 0000 STW5098 control registers 37/85 table 13. cr15 description bits name value cr15 description def. 4-0 da2adg(4:0)* 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 da to ad mixing (audio filter in d/a and a/d path selected) da to ad mixing disabled (default) +2.0 db gain 0.0 db gain -2.0 db gain -4.0 db gain -6.0 db gain -8.0 db gain -10.0 db gain -12.0 db gain -14.0 db gain -16.0 db gain -18.0 db gain -20.0 db gain -22.0 db gain -24.0 db gain -26.0 db gain -28.0 db gain -30.0 db gain -32.0 db gain -34.0 db gain -36.0 db gain -38.0 db gain -40.0 db gain 00000 * when voice filter in d/a or a/d path is selected this function is disabled note: d/a to a/d mixing is performed at ad data rate, so if a/d and d/a rates are different then asynchronous sampling artifacts may occur. control registers STW5098 38/85 table 14. cr16 description bits name value cr16 description def. 5-0 ad2dag(5:0) 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 ad to da mixing (sidetone) ad to da mixing disabled (default) -1.0 db gain -2.0 db gain -3.0 db gain -4.0 db gain -5.0 db gain -6.0 db gain -7.0 db gain -8.0 db gain -9.0 db gain -10.0 db gain -11.0 db gain -12.0 db gain -13.0 db gain -14.0 db gain -15.0 db gain -16.0 db gain -17.0 db gain -18.0 db gain -19.0 db gain -20.0 db gain -21.0 db gain -22.0 db gain -23.0 db gain -24.0 db gain -25.0 db gain -26.0 db gain -27.0 db gain -28.0 db gain -29.0 db gain -30.0 db gain -31.0 db gain -32.0 db gain -33.0 db gain -34.0 db gain -35.0 db gain -36.0 db gain -37.0 db gain -38.0 db gain -39.0 db gain -40.0 db gain -41.0 db gain -42.0 db gain 000000 STW5098 control registers 39/85 5.5 analog functions cr# (hex) descriptiond7d6d5d4d3d2d1d0def. cr17 (11h) mixer switches & mic bias mbias mbiaspd admic adlin mixmic mixlin mixdac miclo 0000 0000 cr18 (12h) input switches x in2vcm linmute linsel(1:0) micmute micsel(1:0) 0010 0100 cr19 (13h) drivers control vcml(1:0) x mutelo mutehp lslim lssel(1:0) 0101 1000 table 15. cr17 description bits name value cr17 description def. 7 mbias 1 0 microphone bias enabled (2.1v typ at mbias pin) microphone bias disabled 0 6 mbiaspd 1 0 mbias pin is pulled down when microphone bias is disabled mbias pin is in high impedance state when microphone bias is disabled 0 5admic 1 0 microphone preamplifiers are connected to ad path microphone preamplifiers are not connected to ad path 0 4adlin 1 0 line in preamplifiers are connected to ad path line in preamplifiers are not connected to ad path 0 3mixmic 1 0 microphone preamplifiers are connected to mixers microphone preamplifiers are not connected to mixers 0 2mixlin 1 0 line in preamplifiers are connected to mixers line in preamplifiers are not connected to mixers 0 1mixdac 1 0 stereo dac path is connected to mixers stereo dac path is not connected to mixers 0 0miclo 1 0 microphone preamplifiers are connected to line out drivers mixers are connected to line out drivers 0 table 16. cr18 description bits name value cr18 description def. 6in2vcm 1 0 unused analog input pins are biased to common mode voltage unused analog input pins are in high impedance state 0 5linmute 1 0 line in preamplifiers are muted line in preamplifiers are not muted 1 4-3 linsel(1:0) 00 01 10 11 input pins connected to line in preamplifiers (if linmute=0) linein (lineinl, lineinr) aux1 (aux1l, aux1r) aux2 (aux2lp-aux2ln, aux2rp-aux2rn) aux3 (aux3l, aux3r) 00 control registers STW5098 40/85 2micmute 1 0 microphone preamplifiers are muted microphone preamplifiers are not muted 1 1-0 micsel(1:0) 00 01 10 11 input pins connected to microphone preamplifiers (if micmute=0) mic (miclp-micln, micrp-micrn) aux1 (aux1l, aux1r) aux2 (aux2lp-aux2ln, aux2rp-aux2rn) aux3 (aux3l, aux3r) 00 table 17. cr19 description bits name value cr19 description def. 7-6 vcml(1:0) 00 01 10 11 common mode voltage level for line out and headphones drivers 1.20 v 1.35 v (default) 1.50 v 1.65 v 01 4mutelo 1 0 line out drivers are muted line out drivers are not muted 1 3mutehp 1 0 headphones drivers (hp) are muted headphones drivers (hp) are not muted 1 2 1earlim 1 0 ear/ls driver gain is limited when v ccls is above 4.2v typ ear/ls driver (ls) gain is not limited 0 2lslim 1-0 1earsel(1:0) 00 01 10 11 mute loudspeaker driver (ls) is muted right right channel mixer only connected to loudspeaker driver left left channel mixer only connected to loudspeaker driver mono (left + right)/2 channel mixers connected to loudspeaker driver 00 2lssel(1:0) table 16. cr18 description bits name value cr18 description def. STW5098 control registers 41/85 5.6 digital audio interfaces master mode and clock generators cr# (hex) descriptiond7d6d5 d4 d3d2d1d0def. cr20 (14h) daock frequency lsb daockf(7:0) 0000 0000 cr21 (15h) daock frequency msb daockf(15:8) 0000 0000 cr22 (16h) da clock generator control x x damast da mastgen end ock dao ck512 dapcmf(1:0) 0000 0000 cr23 (17h) adock frequency lsb adockf(7:0) 0000 0000 cr24 (18h) adock frequency msb adockf(15:8) 0000 0000 cr25 (19h) ad clock generator control x x admast ad mastgen ena dock ado ck512 adpcmf(1:0) 0000 0000 table 18. cr21-20 and cr24-23 description bits name cr21-20 name cr24-23 value cr21-20 and cr24-23 description def. 15-0 daockf(15:0) adockf(15:0) k the following formulas can be used to obtain the value of k for the desired fs or ock respectively in the clock generator fs: data rate (da_sync or ad_sync frequency in master mode) ock: oversampled clock frequency (da_ock or ad_ock) amck: input master clock frequency mckcoeff: see cr30 for definition osr: see bit 2 in cr22 and cr25 0000h note: cr21-20 and cr24-23 are meaningful in master mode only. kfs () round 2 25 fs amck mckcoeff ? -------------------------------------------------------------- ?? ?? = kock () round 2 25 ock amck mckcoeff osr ? ? ----------------------------------------------------------------------------------- - ?? ?? = table 19. cr22 and cr25 description bits name cr22 (name cr25) value cr22 and cr25 description def. 5 damast (admast) 1 0 da (ad) audio interface is in master mode (low impedance output) da (ad) audio interface is in slave mode (high impedance input) 0 4 damastgen (admastgen) 1 0 da (ad) master generator is enabled da (ad) master generator is disabled 0 3 endaock (enadock) 1 0 da_ock (ad_ock) output clock is enabled da_ock (ad_ock) output clock is disabled 0 control registers STW5098 42/85 2 daock512 (adock512) 1 0 definition of da_osr (ad_osr) da_ock/da_sync (ad_ock/ad_sync) ratio in master mode is 512 da_ock/da_sync (ad_ock/ad_sync) ratio in master mode is 256 0 1-0 dapcmf(1:0) (adpcmf(1:0)) 00 00 01 10 11 11 da_ck/da_sync (ad_ck/ad_sync) ratio in pcm master mode - 16 when cr26 dawl=000 (cr27 adwl=000) - 32 when cr26 dawl 000 (cr27 adwl 000) - 64 - 128 - 256 when cr22 daock512=0 (cr25 adock512=0) - 512 when cr22 daock512=1 (cr25 adock512=1) 00 table 19. cr22 and cr25 description bits name cr22 (name cr25) value cr22 and cr25 description def. STW5098 control registers 43/85 5.7 digital audio interfaces cr# (hex) descriptiond7d6d5d4d3d2d1d0def. cr26 (1ah) dac data if control x daform(2:0) daspim dawl(2:0) 0000 0000 cr27 (1bh) adc data if control adrtol adform2:0) adspim adwl(2:0) 0000 0000 cr28 (1ch) dac&adc data if control amckinv dackp dasyncp damono adckp ad syncp admono adhiz 0000 0000 table 20. cr26 description bits name value cr26 description def. 6-4 daform(2:0) 000 001 010 011 100 111 da audio interface format selection delayed format (i 2 s compatible) left aligned format right aligned format dsp format spi format pcm format (uses left channel) 000 3 daspim 1 0 da interface in spi mode receives one word for both channels da interface in spi mode receives two words (alternated, left channel first) 0 2-0 dawl(2:0) 000 001 010 011 100 da interface word length 16 bit 18 bit 20 bit 24 bit 32 bit 000 table 21. cr27 description bits name value cr27 description def. 7adrtol 1 0 ad right channel sent to pcm i/f (must set enadcr=0 in cr1) normal operation 0 6-4 adform(2:0) 000 001 010 011 100 111 ad audio interface format selection delayed format (i 2 s compatible) left aligned format right aligned format dsp format spi format pcm format (sends out left channel) 000 control registers STW5098 44/85 3 adspim 1 0 ad interface in spi mode sends one channel (left) ad interface in spi mode sends two channels (alternated, left first) 0 2-0 adwl(2:0) 000 001 010 011 100 ad interface word length 16 bit 18 bit 20 bit 24 bit 32 bit 000 table 22. cr28 description bits name value cr28 description def. 7amckinv 1 0 amck is inverted amck is not inverted 0 6dackp 1 0 da bit clock pin (da_ck) polarity is inverted da bit clock pin (da_ck) polarity is not inverted 0 5 dasyncp 1 0 dsp and pcm formats in da interface non delayed format delayed format 0 1 0 delayed, left-aligned, right-aligned and spi formats in da interface da sync pin (da_sync) polarity is inverted da sync pin (da_sync) polarity is not inverted 4damono 1 0 mono mode: (l+r)/2 from audio interface is used on both dac channels stereo mode 0 3 adckp 1 0 ad bit clock pin (ad_ck) polarity is inverted ad bit clock pin (ad_ck) polarity is not inverted 0 2 adsyncp 1 0 dsp and pcm formats in ad interface non delayed format delayed format 0 1 0 delayed, left-aligned, right-aligned and spi formats in ad interface da sync pin (da_sync) polarity is inverted da sync pin (da_sync) polarity is not inverted 1admono 1 0 mono mode: (l+r)/2 from adc is sent to both channels in the audio interface stereo mode 0 0 adhiz 1 0 ad data pin (ad_data) is in high impedance state when no data is available ad data pin (ad_data) is forced to 0 when no data is available 0 table 21. cr27 description (continued) bits name value cr27 description def. STW5098 control registers 45/85 5.8 digital filters, software reset and master clock control cr# (hex) descriptiond7d6d5d4d3d2d1d0def. cr29 (1dh) digital filters control x davoice da96k rxnh advoice ad96k adnh txnh 0000 0000 cr30 (1eh) soft reset & amck range swres x x x amcksin ckrange(2:0) 0000 0000 table 23. cr29 description bits name value cr29 description def. 6davoice 1 0 da path voice rx filter is enabled (single channel, left used) da path voice filters are enabled 0 5da96k 1 0 da path data rate is in the range 88 khz to 96 khz da path data rate is in the range 8 khz to 48 khz 0 4rxnh 1 0 da path high pass voice rx filter is disabled da path high pass voice rx filter is enabled (300hz @ 8khz rate) 0 3advoice 1 0 ad path voice tx filter is enabled (single channel, left used) ad path audio filters are enabled 0 2ad96k 1 0 ad path data rate is in the range 88 khz to 96 khz ad path data rate is in the range 8 khz to 48 khz 0 1 adnh 1 0 ad path audio dc filter is disabled ad path audio dc filter is enabled 0 0txnh 1 0 ad path high pass voice tx filter is disabled ad path high pass voice tx filter is enabled (300hz @ 8khz rate) 0 table 24. cr30 description bits name value cr30 description def. 7swres 1 0 software reset: all registers content is reset to the default value control register content is left unchanged 0 3 amcksin 1 0 signal at amck pin is a sinusoid signal at amck pin is a square wave 0 2-0 ckrange(2:0) 000 001 010 011 100 101 amck range mckcoeff 4.0 mhz to 6.0 mhz 8.0 6.0 mhz to 8.0 mhz 6.0 8.0 mhz to 12.0 mhz 4.0 12.0 mhz to 16.0 mhz 3.0 16.0 mhz to 24.0 mhz 2.0 24.0 mhz to 32.0 mhz 1.5 000 control registers STW5098 46/85 5.9 interrupt control and control interface spi out mode note: value at irq pin is: cr# (hex) descriptiond7d6d5d4d3d2d1d0def. cr31 (1fh) interrupt mask vlshen push ben hsdeten vlshmsk push bmsk hsdet msk ovfmsk pormsk 0000 0000 cr32 (20h) interrupt status vlsh pushb hsdet vlshev pushbev hsdetev ovfev porev 0000 0000 cr33 (21h) misc. control x x spiohiz spiosel(1:0) irqcmos ovfda ovfad 0000 0000 table 25. cr31 description bits name value cr31description def. 7vlshen 1 0 vlsh status can be seen at irq output vlsh status is masked 0 6 pushben 1 0 pushb status can be seen at irq output pushb status is masked 0 5 hsdeten 1 0 hsdet status can be seen at irq output hsdet status is masked 0 4vlshmsk 1 0 vlsh event can be seen at irq output vlsh event is masked 0 3 pushbmsk 1 0 pushb event can be seen at irq output pushb event is masked 0 2 hsdetmsk 1 0 hsdet event can be seen at irq output hsdet event is masked 0 1ovfmsk 1 0 ovf event can be seen at irq output ovf event is masked 0 0pormsk 1 0 por event can be seen at irq output por event is masked 0 table 26. cr32 description bits name read only cr32 description def. 7vlsh* 1 0 v ccls is above 4.2 v v ccls is below 4.0 v 0 6 pushb* 1 0 headset button is pressed headset button is released 0 5 hsdet* 1 0 headset connector is inserted headset connector is not inserted 0 irq (1 or z) when (cr31 & cr32) = 00 hex 0 when (cr31 & cr32) 00 hex ? ? ? = STW5098 control registers 47/85 4vlshev 1 0 vlsh bit has changed vlsh bit has not changed 0 3 pushbev 1 0 headset button status has changed headset button status has not changed 0 2 hsdetev 1 0 headset connector status has changed headset connector status has not changed 0 1 ovfev 1 0 an audio data overflow has occurred in dsp no audio data overflow has occurred in dsp 0 0porev 1 0 device was reset by power-on-reset device was not reset by power-on-reset 0 note: content of bits 4 to 0 in cr32 is cleared after reading, while it is left unchanged if accessed for writing. *bits 7 to 5 represent the status when the contro l register is read, not when the event occurred. table 26. cr32 description (continued) bits name read only cr32 description def. table 27. cr33 description bits name val. cr33 description def. 5 spiohiz 1 0 spi control interface out pin is set to high impedance state when inactive spi control interface out pin is set to zero when inactive 0 4-3 spiosel(1:0) 00 01 10 11 out pin selection for spi control interface no output. control registers cannot be read in spi mode spi output sent to irq pin spi output sent to da_ock pin spi output sent to ad_ock pin 00 2 irqcmos 1 0 irq interrupt request pin is set to cmos (active low) irq interrupt request pin is set to pull down 0 1ovfda 1 0 an overflow (saturation) occurred in da path no overflow occurred in da channel 0 0 ovfad 1 0 an overflow (saturation) occurred in ad path no overflow occurred in ad channel 0 note: content of bits 1 to 0 in cr33 is cleared after reading, while it is left unchanged if accessed for writing. control registers STW5098 48/85 5.10 agc cr# (hex) descriptiond7d6d5d4d3d2d1d0def. cr34 (22h) agc attack/decay coeff. agcatt(3:0) agcdec(3:0) 0000 0000 cr35 (23h) agc control x enag clin enag cmic agc range agclev(3:0) 0000 0000 table 28. cr 34 description bits name value cr 34 description def. 7-4 agcatt(3:0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 agc attack time constant; fs=ad data rate 0000 audio filter in ad path 4096 / fs 2048 / fs 1365 / fs 1024 / fs 683 / fs 512 / fs 341 / fs 256 / fs 171 / fs 128 / fs 85 / fs 64 / fs 43 / fs 32 / fs voice filter in ad path 8192 / fs 4096 / fs 2731 / fs 2048 / fs 1365 / fs 1024 / fs 683 / fs 512 / fs 341 / fs 256 / fs 171 / fs 128 / fs 85 / fs 64 / fs 3-0 agcdec(3:0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 agc decay time constant; fs=ad data rate 0000 audio filter in ad path 65536 / fs 32768 / fs 21845 / fs 16384 / fs 10923 / fs 8192 / fs 5461 / fs 4096 / fs 2731 / fs 2048 / fs 1365 / fs 1024 / fs 683 / fs 512 / fs 341 / fs 256 / fs voice filter in ad path 131072 / fs 65536 / fs 43691 / fs 32768 / fs 21845 / fs 16384 / fs 10923 / fs 8192 / fs 5461 / fs 4096 / fs 2731 / fs 2048 / fs 1365 / fs 1024 / fs 683 / fs 512 / fs STW5098 control registers 49/85 table 29. cr 35 description bits name value cr35 description def. 6enagclin 1 0 agc control on ad path acts on line in gain agc control on ad path does not act on line in gain 0 5enagcmic 1 0 agc control on ad path acts on mic gain agc control on ad path does not act on mic gain 0 4 agcrange 1 0 agc action range is -21.0 db to +21.0 db agc action range is -10.5 db to +10.5 db 0 3-0 agclev(3:0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 agc requested output level -30.0 db gain -30.0 db gain -27.0 db gain -24.0 db gain -21.0 db gain -18.0 db gain -15.0 db gain -12.0 db gain -9.0 db gain -6.0 db gain 0000 control interface and master clock STW5098 50/85 6 control interface and master clock unless specified, the following description applies to both entities. 6.1 control interface i 2 c mode figure 5. control interface i 2 c format note: cmod pin tied to gnd figure 6. control interface: i 2 c format timing write single byte start device address reg n address reg n data in ack ack ack stop write multi byte start device address reg n address reg n data in ack ack ack stop reg n+m data in ack m+1 data bytes current addr start device address current reg data out ack no ack stop read single byte current addr start device address current reg data out ack no ack stop read multi byte curr reg+m data out ack ack ack m+1 data bytes start device address reg n address ack ack start device address reg n data out ack no ack stop random addr read single byte random addr read multi byte start device address reg n address ack ack start device address no ack stop reg n+m data out ack ack m+1 data bytes reg n data out ack 001101as 1 001101as 1 001101as 0 001101as 0 001101as 1 001101as 1 001101as 0 001101as 0 (sto) t su (sta) t su (sta) t hd (dat) t su t high t buf (dat) t hd t f t r t low (sta) t hd p s p s r p=stop s = start sr = start repeated sda sclk STW5098 control interface and master clock 51/85 6.2 control interface spi mode figure 7. control interface spi format (a) table 30. control interface timing with i2c format symbol parameter test conditions min. typ. max. unit f scl clock frequency 400 khz t high clock pulse width high 600 ns t low clock pulse width low 1300 ns t r sda and sclk rise time 1000 ns t f sda and sclk fall time 300 ns t hd:sta start condition hold time 600 ns t su:sta start condition setup time 600 ns t hd:dat data input hold time 0 ns t su:dat data input setup time 250 ns t su:sto stop condition setup time 600 ns t buf bus free time 1300 ns a. cmod pin tied to v ccio ; sdo pin position selected with bits spiosel in cr33. a6 a5 8 bit address a4 a3 a2 a1 a0 w/r d7 d6 d5 d4 d3 d2 d1 d0 8 bit data sdin d7 d6 d5 d4 d3 d2 d1 d0 8 bit data sdo sclk csb spiohiz=1 control interface and master clock STW5098 52/85 figure 8. control interface: spi format timing tddo tddol tddof spiohiz=0 spiohiz=1 tscsf thsck tlsck tsdi thdi tscsr t hics sdin sdo sclk csb 15 8 0 w/r d7 d7 d0 d0 tpsck thcs table 31. control interface signal timing with spi format symbol parameter test conditions min. typ. max. unit t hics csb pulse width high 80 ns t scsr setup time csb rising edge to sclk rising edge 20 ns t scsf setup time csb falling edge to sclk rising edge 20 ns t hcs hold time csb rising edge from sclk rising edge 20 ns t sdi setup time sdin to sclk rising edge 20 ns t hdi hold time sdin from sclk rising edge 20 ns t ddof sdo first delay time from sclk falling edge 30 ns t ddo sdo delay time from sclk falling edge 20 ns t ddol sdo delay time from csb rising edge 30 ns t psck period of sck 100 ns t hsck sck pulse width high measured from v ih to v ih 40 ns t lsck sck pulse width low measured from v il to v il 40 ns STW5098 control interface and master clock 53/85 6.3 master clock timing table 32. amck timing symbol parameter amck range min. typ. max. unit t ckdc amck d uty cycle 4 mhz -8 mhz 8 mhz -32 m hz 45 40 55 60 % % audio interfaces STW5098 54/85 7 audio interfaces information included in the following section is valid for both entities. figure 9. audio interfaces formats: delayed, left and right justified 1 2 n-1 n msb lsb 1 2 n-1 n msb lsb 1 2 n-1 n msb lsb 1 2 n-1 n msb lsb 1 ad_ck/da_ck 1 ad_ck/da_ck n-bit word left data i2s format (delayed) with default polarity settings, adhiz=0 left justified format with default polarity settings, adhiz=0 n-bit word left data n-bit word right data n-bit word right data 1 2 n-1 n msb lsb 1 2 n-1 n msb lsb 1 2 n-1 n msb lsb 1 2 n-1 n msb lsb n-bit word left data n-bit word left data n-bit word right data n-bit word right data 1 2 n-1 n msb lsb 1 2 n-1 n msb lsb 1 2 n-1 n msb lsb 1 2 n-1 n msb lsb n-bit word left data right justified format with default polarity settings n-bit word left data n-bit word right data n-bit word right data 32 ad_ck/da_ck 32 ad_ck/da_ck da_sync/ ad_sync da_data ad_data da_ck/ ad_ck da_sync/ ad_sync da_data ad_data da_ck/ ad_ck da_sync/ ad_sync da_data ad_data da_ck/ ad_ck STW5098 audio interfaces 55/85 figure 10. audio interfaces formats: dsp, spi and pcm da_sync/ 1 2 n-1 n msb lsb ad_sync 1 2 n-1 n msb lsb 1 2 n-1 n msb lsb 1 2 n-1 n msb lsb n-bit word left data dsp format delayed and non-delayed (default ad_ck/da_ck polarity, adhiz=0) spi format (slave only) (default ad_ck/da_ck polarity, adhiz=1 - stereo or mono) n-bit word left data n-bit word right data n-bit word right data 1 2 n-1 n msb lsb 1 2 msb n-bit word left/mono data n-bit word right/mono data pcm format (default ad_ck/da_ck polarity, adhiz=1) 3 3 1 2 n-1 n msb lsb 1 2 msb n-bit word left/mono data n-bit word right/mono data 3 3 1 2 n-1 n msb lsb n-bit word mono data 3 1 2 n-1 msb lsb n-bit word mono data 3 high impedance 1 msb 1 msb x high impedance x syncp=0 syncp=1 { da_data ad_data da_ck/ ad_ck da_sync/ ad_sync da_data ad_data da_ck/ ad_ck da_sync/ ad_sync syncp=0 syncp=1 { da_data ad_data da_ck/ ad_ck n audio interfaces STW5098 56/85 figure 11. audio interface timings: master mode figure 12. audio interface timing: slave mode adhiz=0 adhiz=0 adhiz=1 adhiz=1 adhiz=0 adhiz=1 adhiz=0 adhiz=1 tdsy tsdda thdda tdad ckp=0 ckp=1 tdad tdadz da_sync/ ad_sync da_ck/ ad_ck da_data { tdad pcm format only ad_data ad_data all other formats adhiz=0 adhiz=0 adhiz=1 adhiz=1 adhiz=0 adhiz=1 adhiz=0 tdadst thck tlck tpck tssy da_sync/ tsdda thdda thsy ad_sync tdad ckp=0 ckp=1 tdadz da_ck/ ad_ck da_data { tdad tdad pcm format ad_data ad_data all other formats adhiz=1 STW5098 audio interfaces 57/85 table 33. audio interface signal timings symbol parameter test conditions min. typ. max. unit t dsy delay of ad_sync/da_sync edge from ad_ck/da_ck active edge master mode 10 ns t sdda setup time da_data to da_ck active edge 10 ns t hdda hold time da_data from da_ck active edge 10 ns t dad delay of ad_data edge from ad_ck active edge 30 ns t dadst delay of the first ad_data edge from ad_sync active edge ad_sync active edge comes after ad_ck active edge 30 ns t dadz delay of ad_data high impedance from ad_sync inactive edge pcm format 10 50 ns t ssy setup time ad_sync/da_sync to ad_ck/da_ck active edge slave mode 20 ns t hsy hold time ad_sync/da_sync from ad_ck/da_ck active edge slave mode 20 ns t pck period of ad_ck/da_ck slave mode 100 ns t hck ad_ck/da_ck pulse width high measured from v ih to v ih 40 ns t lck ad_ck/da_ck pulse width low measured from v il to v il 40 ns timing specifications STW5098 58/85 8 timing specifications information included in this section is valid for both entities. unless otherwise specified, v ccio = 1.71v to 2.7v, t amb = -30c to 85c, max capacitive load 20 pf; typical characteristics are specified at v ccio = 2.4 v, t amb = 25 c; all signals are referenced to gnd, see note below figure for timing definitions. figure 13. a.c. testing input-output waveform note: a signal is valid if it is above v ih or below v il and invalid if it is between v il and v ih . for the purpose of this specification the following conditions apply (see figure 13 above): a) all input signal are defined as: v il =0.2 ? v ccio , v ih =0.8 ? v ccio , t r < 10ns, t f < 10ns. b) delay times are measured from the inputs signal valid to the output signal valid. c) setup times are measured from the data input valid to the clock input invalid. d) hold times are measured from the clock signal valid to the data input invalid. note: all timing specifications subject to change. ac testing: inputs are driven at 0.8 ? v ccio for a logic ?1? and 0.2 ? v ccio for a logic ?0?. timing measurements are made at 0.7 ? v ccio for a logic ?1? and 0.3 ? v ccio for a logic ?0?. test points 0.72vccio 0.32vccio 0.72vccio 0.32vccio 0.82vccio 0.22vccio input/output STW5098 operative ranges 59/85 9 operative ranges 9.1 absolute maximum ratings 9.2 operative supply voltage table 34. absolute maximum ratings parameter value unit v cc or v ccio to gnd -0.5 to 3.6 v v cca or v ccp to gnd -0.5 to 5 v v ccls to gnd -0.5 to 7 v voltage at analog inputs (v cca 3.3v) gnd-0.5 to v cca +0.5 v maximum power delivered to the load from lsp/n 500 mw peak current at hpr,hpl 100 ma current at v ccp , v ccls , gndp 350 ma current at any digital output 50 ma voltage at any digital input (v ccio 2.7v); limited at 50ma gnd-0.5 to v ccio +0.5 v storage temperature range -65 to 150 c operating temperature range (1) -30 to 85 c electrostatic discharge voltage (vesd) human body model (2) charge device model (3) -2 to +2 -500 to +500 kv v 1. in some operating conditions the te mperature can be limited to 70 c. s ee loudspeaker driver description from section 4.10 for details. 2. hbm tests have been performed in compliance with jesd22-a114-b and esd stm 5.1-2001.hbm 3. cdm tests have been performed in compliance with cdm ansi-esdstm5.3.1-1999 table 35. operative supply voltage symbol parameter condition min. max. unit v cc digital supply 1.71 2.7 v v cca analog supply note: v cca v cc a24v=0 (bit 1 in cr0) a24v=1 (bit 1 in cr0) 2.7 2.4 3.3 2.7 v v v ccio digital i/o supply d12v=0 (bit 0 in cr0) d12v=1 (bit 0 in cr0) 1.71 1.2 v cc 1.8 v v v ccp stereo power drivers supply v cca 3.3 v v ccls mono power driver supply v cca 5.5 v v g single supply voltage range v cc = v cca = v ccio = v ccp = v ccls a24v=1 (bit 1 in cr0) 2.4 2.7 v operative ranges STW5098 60/85 9.3 power dissipation unless otherwise specified, v ccp =v ccls =v cca = 2.7v to 3.3v, v ccio =v cc = 1.71v to 2.7v, t amb = -30c to 85c, all analog outputs not loaded; typical characteristics are specified at v ccio =v cc = 1.8v, v ccp =v ccls =v cca =2.7v, t amb =25c. 9.4 typical power dissipation by entity t amb = 25c; analog supply: v ccp =v ccls =v cca =2.7v; digital supply: v ccio =v cc =1.8v. full scale signal in every path, 20k ? load at analog outputs. no master clock table 36. power dissipation symbol parameter test conditions min. typ. max. unit poff power down dissipation no master clock amck=13mhz 0.8 5.8 w w pad stereo adc power 52.6 mw pda stereo dac power 46.6 mw pdaad stereo adc+dac power 93.8 mw paa stereo analog path power 27.6 mw table 37. typical power dissipation, no master clock n. function cr0-cr2 setting other settings supply current power 1 power down cr0=0x00 cr1=0x00 cr2=0x00 analog: digital: total: 0.02 a 0.20 a 0.05 w 0.36 w 0.41 w 2 stereo analog path (mic-lo) cr0=0xd0 cr1=0x0c cr2=0xc0 miclo=1 micsel=2 analog: digital: total: 4.3 ma 2.0 a 11.6 mw 0.0 mw 11.6 mw 3 stereo analog path (mic-mixer-lo) cr0=0xd0; cr1=0x0c; cr2=0xc3 mixmic=1 micsel=2 analog: digital: total: 5.4 ma 2.0 a 14.6 mw 0.0 mw 14.6 mw STW5098 operative ranges 61/85 master clock amck = 13 mhz table 38. typical power dissipation with master clock amck = 13 mhz n. function cr0-cr2 setting other settings supply current power 4 power down cr0=0x00 cr1=0x00 cr2=0x00 analog: digital: total: 0.02 a 2.20 a 0.05 w 3.96 w 4.01 w 5stereo adc cr0=0xe8 cr1=0xcc cr2=0x00 micsel=1 admic=1 analog: digital: total : 7.9 ma 2.8 ma 21.3 mw 5.0 mw 26.3 mw 6stereo dac cr0=0xe8 cr1=0x30 cr2=0x33 mixdac=1 analog: digital: total: 6.1 ma 3.8 ma 16.5 mw 6.8 mw 23.3 mw 7 stereo analog path (mic-lo) cr0=0xe8 cr1=0x0c cr2=0xc0 miclo=1 micsel=2 analog: digital: total: 4.8 ma 0.8 ma 13.0 mw 1.4 mw 13.8 mw 8 stereo adc stereo dac cr0=0xe8 cr1=0xfc cr2=0x33 micsel=2 admic=1 mixdac=1 analog: digital: total: 13.5 ma 5.8 ma 36.5 mw 10.4 mw 46.9 mw 9 stereo adc stereo dac stereo analog path cr0=0xe8 cr1=0xff cr2=0xf3 linsel=2; micsel=2 adlin=1;mixdac=1 miclo=1 analog: digital: total: 15.2 ma 5.8 ma 41.0 mw 10.4 mw 51.4 mw 10 voice tx+rx cr0=0xe8 cr1=0xa8 cr2=0x06 micsel=2; lsmode=2 admic=1 mixdac=1 advoice=1 davoice=1 v cca ,v ccp : v ccls : digital total: 6.8 ma 1.3 ma 2.5 ma 18.4 mw 5.5 mw 4.5 mw 28.4 mw electrical characteristics STW5098 62/85 10 electrical characteristics unless otherwise specified, v ccio = 1.71v to 2.7v, t amb = -30c to 85c; typical characteristic are specified at v ccio = 2.0v, t amb = 25c; all signals are referenced to gnd. 10.1 digital interfaces note: see figure 13: a.c. testing input-output waveform on page 58 . 10.2 amck with sinusoid input table 39. digital interfaces specifications symbol parameter test conditions min. typ. max. unit v il input low voltage all digital inputs dc ac 0.3 ? v ccio 0.2 ? v ccio v v v ih input high voltage all digital inputs, dc ac 0.7 ? v ccio 0.8 ? v ccio v v v ol output low voltage all digital outputs i l =10 a i l =2 a 0.1 0.4 v v v oh output high voltage all digital outputs i l =10 a i l =2 a v ccio -0.1 v ccio -0.4 v v i il input low current any digital input, gnd < v in < v il -1 1 a i ih input high current any digital input, v ih < v in < v ccio -1 1 a i oz output current in high impedance (tristate) tristate outputs -1 1 a table 40. amck with sinusoid input specifications symbol parameter test conditions min. typ. max. unit c amck minimum external capacitance amcksin=1, see cr30 100 pf v amck amck sinusoidal voltage swing amcksin=1, see cr30 0.5 v ccio v pp STW5098 electrical characteristics 63/85 10.3 analog interfaces information below is for each entity. table 41. analog interface specifications symbol parameter test conditions min. typ. max. unit i mic mic input leakage gnd< v mic < v cca -100 +100 a r mic mic input resistance 30 50 k ? r lin line in input resistance 30 k ? r lhp headphones (hp) drivers load resistance hpl, hpr to gndp or vcmhp 14.4 16/32 ? r lear earphone (ear) drivers load resistance 1 earp to 1earn 30 32 ? r lls loudspeaker (ls) drivers load resistance 2lsp to 2lsn 6.4 8 ? c lhp headphones (hp) drivers load capacitance hpl, hpr to gndp or vcmhp 50 50* pf nf c lear earphone (ear) drivers load capacitance 1 earp to 1earn 50 50* pf nf c lls loudspeaker (ls) drivers load capacitance 2lsp to 2lsn 50 50* pf nf v offls differential offset voltage at 2lsp, 2lsn r l =50 ? -50 +50 mv v offear differential offset voltage at 1earp, 1earn r l =50 ? -50 +50 mv r lol line out (ol) diff./single- ended driver load resistance olp/orp to oln/orn or olp/orp to gnd (decoupled) 1k ? * with series resistor electrical characteristics STW5098 64/85 10.4 headset plug-in and push-button detector information below is for each entity. 10.5 microphone bias information below is for each entity. 10.6 power supply rejection ratio table 42. headset plug-in and push-button detector specifications symbol parameter test conditions min. typ. max. unit hd vl plug-in detected voltage at hdet v cca -1 v hd vh plug-in undetected voltage at hdet v cca -0.5 v hd h plug-in detector hysteresis 100 mv pb vl push-button pressed voltage at hdet 0.5 v pb vh push-button released voltage at hdet 1 v pb d push-button de-bounce time 15 50 ms table 43. microphone bias specifications symbol parameter test conditions min. typ. max. unit v mbias mbias output voltage 1.95 2.1 2.25 v i mbias mbias output current from mbias to ground 1.1 ma r mbias mbias output load 3.5 k ? c mbias mbias output capacitance 150 pf psr mb4 psr mb20 mbias power supply rejection f<4khz f<20khz 60 50 db db table 44. power supply rejection ratio specifications symbol parameter test conditions min. typ. max. unit psr l20 psr l200 psrr v ccls each output (lsp, lsn) f<20khz f<200khz 65 47 db db psr ph psr pos psr pod psrr v ccp headphones f<20khz line out single ended f<20khz line out differential f<20khz 65 65 65 db db db psr am psr al psrr v cca mic input f<20khz line in f<20khz 50 50 db db STW5098 electrical characteristics 65/85 10.7 ls and ear gain limiter information below is for each entity. table 45. ls and ear gain limiter symbol parameter test conditions min. typ. max. unit vls limh high voltage at v ccls (vlsh=1) v ccls raising 4.2 v vls liml low voltage at v ccls (vlsh=0) v ccls falling 4.0 v vls limd v ccls hysteresis 200 mv note: see cr32 for vlsh definition. see loudspeaker driver description in section 4.10 for details. analog input/output operative ranges STW5098 66/85 11 analog input/output operative ranges information included in this section applies to both entities. 11.1 analog levels 11.2 microphone input levels analog supply range: 2.7 v < v cca <3.3v table 46. reference full scale analog levels symbol parameter test conditions min. typ. max. unit 0dbfs level 2.7v < v cca < 3.3v 12 4 dbv pp v pp 0dbfs level low voltage mode 2.4v < v cca < 2.7v 10 3.18 dbv pp v pp table 47. microphone input levels, absolute levels at pins connected to preamplifiers symbol parameter test conditions min. typ. max. unit overload level, single ended mic gain = 0 to 6db 707 2 -6 mv rms v pp dbfs overload level, single ended, versus mic gain mic gain > 6db ? ( mic_gain) dbfs overload level, differential mic gain = 0db 1.41 4 0 mv rms v pp dbfs overload level, differential, versus mic gain mic gain > 0db ? ( mic_gain) dbfs note: when 2.4 v < v cca < 2.7 v, voltage values are reduced by 2db. table 48. microphone input levels, absolute levels at pins connected to the line-in amplifiers symbol parameter test conditions min. typ. max. unit overload level, single ended line in gain from ? 20db to 6db 707 2 -6 mv rms v pp dbfs overload level (single ended) versus line in gain line in gain > 6db ? ( line_in_gain) dbfs overload level (differential) line in gain from ? 20db to 0db 1.41 4 0 mv rms v pp dbfs STW5098 analog input/output operative ranges 67/85 11.3 line output levels analog supply range: 2.7 v < v cca <3.3v 11.4 power output levels hp analog supply range: 2.7 v < v cca <3.3v 11.5 power output levels ls and ear analog supply range: 2.7 v < v cca <3.3v overload level (differential) versus line in gain line in gain > 0db ? ( line_in_gain) dbfs note: when 2.4 v < v cca < 2.7 v, the values are reduced by 2db table 48. microphone input levels, absolute levels at pins connected to the line-in amplifiers symbol parameter test conditions min. typ. max. unit table 49. absolute levels at olp/oln, orp/orn symbol parameter test conditions min. typ. max. unit output level, single ended 0 db gain full scale digital input 707 2 -6 mv rms v pp dbfs output level, differential 0 db gain full scale digital input 1.41 4 0 mv rms v pp dbfs note: when 2.4 v < v cca < 2.7 v, the values are reduced by 2db table 50. absolute levels at hpl - hpr symbol parameter test conditions min. typ. max. unit output level -6db gain full scale digital input 707 2 -6 mv rms v pp dbfs max output power (1) 16 ? load v ccp > 3.2 v 40 mw 1. in some operating conditions the maximum output power can be limited. see ? section 9.1: absolute maximum ratings ? and ?loudspeaker driver? description from section 4.10: analog output drivers for details. note: when 2.4 v < v cca < 2.7 v, the values are reduced by 2db analog input/output operative ranges STW5098 68/85 table 51. absolute levels at 1earp-1earn and 2lsp - 2lsn symbol parameter test conditions min. typ. max. unit output level 0db gain full scale digital input 1.41 4 0 v rms v pp dbfs max ear output power 32 ? load v ccls > 4v 125 mw max ls output power (1) 8 ? load v ccls > 4v 500 mw 1. in some operating conditions the maximum output power can be limited. see ? section 9.1: absolute maximum ratings ? and ?loudspeaker driver? description from section 4.10: analog output drivers for details. note: when 2.4 v < v cca < 2.7 v, the values are reduced by 2db STW5098 stereo audio adc specifications 69/85 12 stereo audio adc specifications information included in this section applies to both entities. typical measures at v cca =v ccp =v ccls =2.7v; v ccio =v cc =1.8 v; tamb=25 c;13 mhz amck table 52. stereo audio adc specifications symbol parameter test conditions min. typ. max. unit adn resolution 20 bits addrm addrli dynamic range 20hz to 20khz, a-weighted measured at -60dbfs mic input, 21db gain line-in, 0db gain 87 89 91 93 db db adsna adsn signal to noise ratio max level at mic input, 21db gain a-weighted unweighted (20 hz to 20 khz) 90 86 db db input referred adc noise a-weighted mic input 0db gain mic input 21db gain mic input 39db gain line in input 0db gain line in input 18db gain 37 3.3 1.9 30 7.5 v v v v v adthd total harmonic distortion max level at mic input, 21db gain 0.001 0.003 % deviation from linear phase measurement bandwidth 20hz to 20khz, fs= 48khz. combined digital and analog filter characteristics 1deg adf pb passband combined digital and analog filter characteristics ad96k=0 00.45fskhz passband ripple combined digital and analog filter characteristics ad96k=0 0.2 db adf sb stopband combined digital and analog filter characteristics ad96k=0 0.55fs khz stopband attenuation measurement bandwidth up to 3.45fs. combined digital and analog filter characteristics, ad96k=0 60 db adt gd group delay audio filters, 96khz fs audio filters, 48khz fs audio filters, 8khz fs 0.11 0.4 2.6 ms ms ms interchannel isolation 90 db interchannel gain mismatch 0.2 db gain error 0.5 db note: when 2.4 v < v cca < 2.7 v, the values are reduced by 2db stereo audio dac specifications STW5098 70/85 13 stereo audio dac specifications information included in this section applies to both entities. typical measures at v cca =v ccp =v ccls =2.7v; v ccio =v cc =1.8v; tamb=25 c;13mhz amck table 53. stereo audio dac specifications symbol parameter test conditions min. typ. max. unit dan resolution 20 bits dadr dynamic range 20hz to 20khz, a-weighted. measured at -60dbfs differential line out single-ended line out hpl/hpr to gnd or vcmhp lsp-lsn 90 95 93 94 94 db db db db dasna dasn signal to noise ratio 2vpp output hpl, hpr gain set to -6db, 16 ? load a-weighted unweighted (20 hz to 20 khz) 94 90 db db dathdl total harmonic distortion worst case load 2v pp output hpl, hpr gain set to -6db, 16 ? load 0.02 0.04 % dathd total harmonic distortion 2v pp output, hpl, hpr gain set to -6db, 1k ? load 0.004 % deviation from linear phase measurement bandwidth 20hz to 20khz, fs= 48khz. combined digital and analog filter characteristics 1deg daf pb passband combined digital and analog filter characteristics, da96k=0 00.45fskhz passband ripple combined digital and analog filter characteristics, da96k=0 0.2 db daf sb stopband combined digital and analog filter characteristics, da96k=0 0.55fs khz stopband attenuation measurement bandwidth up to 3.45fs. combined digital and analog filter characteristics, da96k=0 50 db tsf transient suppression filter cut-off frequency 15 23 hz out of band noise measurement bandwidth 20 khz to 100 khz. zero input signal -85 dbr STW5098 ad to da mixing (sidetone) specifications 71/85 14 ad to da mixing (sidetone) specifications information included in this section applies to both entities. typical measures at v cca =v ccp =v ccls =2.7v; v ccio =v cc =1.8v; tamb=25 c;13mhz amck. dat gd group delay audio filters, 96khz fs audio filters, 48khz fs audio filters, 8khz fs 0.09 0.4 2.6 ms ms ms interchannel isolation 2vpp output hpr, hpl unloaded hpr, hpl with 16 ? to vcmhp 100 60 db db interchannel gain mismatch 0.2 db gain error 0.5 db sut startup time from power up fs=48 khz line out hpl/r out 1 10 ms ms note: when 2.4 v < v cca < 2.7 v, values are reduced by 2 db table 53. stereo audio dac specifications (continued) symbol parameter test conditions min. typ. max. unit table 54. ad to da mixing (sidetone) specifications symbol parameter test conditions min. typ. max. unit stdel ad to da mixing (sidetone) delay valid for audio and voice filters 5 10 s stereo analog-only path specifications STW5098 72/85 15 stereo analog-only path specifications information included in this section applies to both entities. measured at differential line-out, enosc=1, no master clock. typical measures at v cca =v ccp =v ccls =2.7v; v ccio =v cc =1.8v; tamb=25 c table 55. stereo analog-only path specifications symbol parameter test conditions min. typ. max. unit aadrm aadrli dynamic range 20hz to 20khz, a-weighted. measured at -60dbfs mic input, 21db gain line-in, 0db gain 90 90 95 97 db db aasna aasn signal to noise ratio max level at line-in input, 0db gain, a-weighted unweighted (20 hz to 20 khz) 97 94 db db aathd total harmonic distortion 1khz @ 0dbfs mic input, 21db gain line-in input, 0db gain 0.003 0.004 0.01 0.02 % % note: when 2.4v STW5098 typical performance plots 75/85 figure 20. adc 96 khz audio path measured filter response figure 21. adc 96 khz audio in-band measured filter response figure 22. adc voice tx path measured filter response figure 23. adc voice tx path measured in- band filter response figure 24. dac voice (rx) digital filter characteristics figure 25. dac voice (rx) in-band digital filter characteristics the plot is extended down to 5 hz to show the high pass filter implemented in the adc 96 khz sample rate, 96 khz audio filter selected signal from mic input -80 -70 -60 -50 -40 -30 -20 -10 0 10 100 1k 10k 100k gain [db] frequency [hz] 96 khz sample rate, 96 khz audio filter selected signal from mic input. -5 -4 -3 -2 -1 0 1 0 5k 10k 15k 20k 25k 30k 35k 40k 45k gain [db] frequency [hz] 8 khz sample rate, tx voice filter selected. signal from mic input -70 -60 -50 -40 -30 -20 -10 0 100 1k 10k gain [db] frequency [hz] 8 khz sample rate, tx voice filter selected signal from mic input. -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 500 1k 1500 2k 2500 3k 3500 4k gain [db] frequency [hz] 8 khz sample rate, rx voice filter -70 -60 -50 -40 -30 -20 -10 0 100 1k 10k gain [db] frequency [hz] 8 khz sample rate, rx voice filter -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 500 1k 1500 2k 2500 3k 3500 4k gain [db] frequency [hz] typical performance plots STW5098 76/85 figure 26. adc path fft figure 27. adc s/n versus input-level figure 28. dac path fft figure 29. dac s/n versus input-level figure 30. analog path fft figure 31. analog path s/n versus input-level -120 -100 -80 -60 -40 -20 0 0 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k amplitude [dbfs] frequency [hz] 12 mhz master clock. differential input at mic preamplifier, 21 db gain. 48 khz sampling rate. both channels active 20 30 40 50 60 70 80 90 100 -60 -50 -40 -30 -20 -10 0 s/n [db] input level [dbfs] 12 mhz master clock differential input at line-in amplifier, 0 db gain. 48 khz sampling rate a-weighted, both channels active 12 mhz master clock. 48 khz sampling rate differential output at line-out, 1k ? load. both channels active -120 -100 -80 -60 -40 -20 0 0 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k amplitude [dbfs] frequency [hz] 20 30 40 50 60 70 80 90 100 -60 -50 -40 -30 -20 -10 0 s/n [db] input level [dbfs] 12 mhz master clock. 48 khz sampling rate differential output at line-out, 1k ? load. a-weighted, both channels active -120 -100 -80 -60 -40 -20 0 0 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k amplitude [dbfs] frequency [hz] differential input at mic preamplifier, 21 db gain. direct mic to line-out connection (miclo=1) differential output at line-out, 20k ? load. both channels active 20 30 40 50 60 70 80 90 100 -60 -50 -40 -30 -20 -10 0 s/n [db] input level [dbfs] differential input at line-in amplifier, 0 db gain. line-in to da-mixer to line-out connection. differential output at line-out, 20k ? load. a-weighted, both channels active STW5098 package mechanical data 77/85 18 package mechanical data in order to meet environmental requirements, st offers these devices in ecopack? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com. package mechanical data STW5098 78/85 18.1 lfbga 6x6x1.4 note: 1 lfbga stands for low profile fine pitch ball grid array. - low profile: the total profile height (dim a) is measured from the seating plane to the top of the component. the maximum total package height is calculated as follows: . fine pitch: e<1.0 mm pitch 2 the typical ball diameter before mounting is 0.30 mm 3 the tolerance of position that controls the location of the pattern of balls with respect to datum a and b. for each ball there is a cylindrical tolerance zone eee perpendicular to datum c and located on true position with respect to datum a and b as defined by e. the axis perpendicular to datum c of each ball must lie within this tolerance zone. 4 the tolerance of position that controls the location of the balls within the matrix with respect to each other. for each ball there is a cylindrical tolerance zone fff perpendicular to datum c and located on true position as defined by e. the axis perpendicular to datum c of each ball must lie within this tolerance zone. each tolerance zone fff in the array is contained entirely in the respective zone eee above. the axis of each ball must lie simultaneously in both tolerance zones. 5 the terminal a1 corner must be identified on the top surface by using a corner chamfer, ink or metallized markings, or other feature of package body or integral heatslug. a distinguishing feature is allowable on the bottom surface of the package to identify the terminal a1 corner. exact shape of each corner is optional. table 57. dimensions of lfbga 6x6x1.4 112 4r11x11. 0.5 reference databook (mm) drawing (mm) notes min. typ. max. min. typ. max. a 1.40 1.26 note 1 a1 0.15 0.16 0.21 0.26 a2 0.985 0.93 0.985 1.04 a3 0.20 0.16 0.20 0.24 a4 0.80 0.77 0.785 0.80 b 0.25 0.30 0.35 0.25 0.30 0.35 note 2 d 5.85 6.00 6.15 5.90 6.00 6.10 d1 5.00 5.00 e 5.85 6.00 6.15 5.90 6.00 6.10 e1 5.00 5.00 e0.50 0.50 f0.50 0.50 ddd 0.08 0.08 eee 0.15 0.15 note 4 fff 0.05 0.05 note 5 a2typ a1typ a ( 1 2 a3 2 a4 2 + + tolerancevalues ) + + STW5098 package mechanical data 79/85 figure 32. lfbga 6x6x1.4 112 4r11x11 0.5 drawing f ef d1 e1 e e d c b a 12345678 a1 corner index area (see note 3) ?b (112 balls) bottom view k j i e d g f h 91011 c a2 plane seating ddd c a1 a package mechanical data STW5098 80/85 18.2 vfbga 5x5x1.0 note: 1 vfbga stands for very thin profile fine pitch ball grid array. the maximum total package height is calculated by the following methodology: . very thin profile: max/fine pitch: e<1.0 mm 2 the typical ball diameter before mounting is 0.25 mm 3 vfbga with 0.40mm ball pitch is not yet registered into jedec publications. 4 the tolerance of position that controls the location of the pattern of balls with respect to datum a and b. for each ball there is a cylindrical tolerance zone eee perpendicular to datum c and located on true position with respect to datum a and b as defined by e. the axis perpendicular to datum c of each ball must lie within this tolerance zone. 5 the tolerance of position that controls the location of the balls within the matrix with respect to each other. for each ball there is a cylindrical tolerance zone fff perpendicular to datum c and located on true position as defined by e. the axis perpendicular to datum c of each ball must lie within this tolerance zone. each tolerance zone fff in the array is contained entirely in the respective zone eee above. the axis of each ball must lie simultaneously in both tolerance zones. 6 the terminal a1 corner must be identified on the top surface by using a corner chamfer, ink or metallized markings, or other feature of package body or integral heatslug. a distinguishing feature is allowable on the bottom surface of the package to identify the terminal a1 corner. exact shape of each corner is optional. table 58. dimensions of vfbga 5x5x1.0 112 balls 0.4 mm pitch reference databook (mm) drawing (mm) notes min. typ. max. min. typ. max. a 1.00 0.99 note 1 a1 0.125 0.125 0.165 0.205 a2 0.765 0.71 0.765 0.82 a3 0.18 0.14 0.18 0.22 a4 0.60 0.57 0.585 0.60 b 0.22 0.26 0.30 0.22 0.26 0.30 note 2 d 4.95 5.00 5.05 4.95 5.00 5.05 d1 4.00 4.00 e 4.95 5.00 5.05 4.95 5.00 5.05 e1 4.00 4.00 e0.40 0.40 note 3 f0.50 0.50 ddd 0.08 0.08 eee 0.13 0.13 note 4 fff 0.04 0.04 note 5 a2typ a1typ a ( 1 2 a3 2 a4 2 + + tolerancevalues ) + + 0.80mm a 1.00mm < STW5098 package mechanical data 81/85 figure 33. vfbga 5x5x1.0 112 0.4 drawing application schematics STW5098 82/85 19 application schematics see figure 34: STW5098 application schematics . STW5098 application schematics 83/85 figure 34. STW5098 application schematics 1 uf / 0402 microphone jack audio a loudspeaker 1 loudspeaker 2 mono speaker 220 nf / 0406 220 nf / 0406 220 nf / 0406 1 uf / 0402 220 nf / 0406 2 . 2 u f / 0 6 0 3 220 nf / 0406 220 nf / 0406 220 nf / 0406 ? ? 22uf / 0805 22uf / 0805 1 uf / 0402 220ohm r815 2 1 c801 1nf c811 680nf 2 1 audio_2v8 2.7kohm r808 r812 22kohm 1uf c839 100nf 100nf c804 c803 100nf c805 c806 100nf 100nf c826 vbat 680nf c820 2 1 r816 220ohm audio_1v8 1nf c840 22kohm r809 c842 22pf c846 1nf 2 1 hp802 j800 jack_cui st000000144 1 1 3 2 2 3 4 4 c821 680nf 1.2kohm r807 c 8 1 3 2 . 2 n f 100nf c831 c830 100nf 10uf c833 2 1 1 0 k o h m r 8 0 0 100nf c832 100nf c808 hp801 a u d i o _ 2 v 8 tp806 c827 33uf 2 1 100nf c829 680nf c809 2 1 audio_2v8 22pf c845 c814 100nf c844 22pf 100nf c835 c837 1uf 2 1 c818 100nf 100nf c802 c834 100nf 100nf c810 v b a t vbat r814 22kohm 100nf c836 c812 100nf 100nf c824 c823 100nf audio_1v8 c828 100nf 22pf c841 22pf c843 100nf c822 100nf c825 hp800 c139 100nf audio_1v8 tp809 33uf c807 2 1 r810 1.2kohm r811 2.7kohm 470nf c815 c3 v c c 1 a5 v c c 2 b6 a3 vout1m vout1p b4 e3 vout2m vout2p d4 c816 100nf mn801 ts4984 st000000133 bypass1 c1 bypass2 c5 gnd1 d2 e1 gnd2 in1m a1 in1p b2 in2m e5 in2p d6 stdby 22kohm r813 audio_1v8 c800 100nf 1 0 k o h m r 8 0 2 gndp4 vcc1 b8 d4 vcc2 vcca1 c1 vcca2 c3 d9 vcca3 vccio d5 vccls1 i8 j5 vccls2 j9 vccls3 h7 vccp1 vccp2 j2 k1 vccp3 vccp4 k10 h9 i9 2orp b2 2sclk a4 2sda_sdin 2vcmhp k4 j4 2vcmhps b7 amck a1 gnd1 b11 gnd2 gnda1 f3 g8 gnda2 gndcm1 h4 j1 gndcm2 j6 gndp1 gndp2 j7 gndp3 j11 k2 2hpl 2hpr k11 c9 2irq g4 2lineinl 2lineinr h10 2lsn k8 k9 2lsns k6 2lsp k5 2lsps c10 2mbias e4 2micln f4 2miclp e11 2micrn f11 2micrp 2oln h3 2olp i3 2orn 2aux1r g2 2aux2ln h2 2aux2lp g11 2aux2rn h11 2aux2rp e1 2aux3l e10 2aux3r e8 2caplinein k7 2capls f1 2capmic c4 2cmod b6 2da_ck b10 2da_data b5 2da_ock b9 2da_sync b1 2hdet i4 1micrn f9 1micrp 1oln i1 i2 1olp 1orn i10 j10 1orp a2 1sclk c5 1sda_sdin 1vcmhp i5 k3 1vcmhps c6 2ad_ck a8 2ad_data b3 2ad_ock a9 2ad_sync a7 2as_csb d1 2aux1l d11 1da_data a5 1da_ock a10 1da_sync 1hdet c2 1hpl j3 h8 1hpr d8 1irq 1lineinl g3 i11 1lineinr 1lsn i7 1lsns j8 h6 1lsp h5 1lsps c11 1mbias d3 1micln e3 1miclp e9 1ad_ock c8 1ad_sync d7 1as_csb d2 1aux1l d10 1aux1r 1aux2ln g1 1aux2lp h1 1aux2rn g10 g9 1aux2rp e2 1aux3l 1aux3r f10 1caplinein f8 i6 1capls f2 1capmic b4 1cmod d6 1da_ck a11 st000000131 STW5098 mn800 a6 1ad_ck c7 1ad_data a3 100nf c838 100nf c817 c819 100nf m800 1 2 d801 transil st000000145 2 gnd1 gnd2 5 i_o1 1 i_o2 34 i_o3 i_o5 6 audio_earkit_right_speaker audio_earkit_left_speaker audio_jack_detect audio_handset_mic_n audio_handset_mic_p audio_pwr_amplifier_standby 5 audio_to_tvout_r audio_to_tvout_l audio_fm_antenna 5 5 audio_from_modem_n audio_from_modem_p audio_fm_right audio_fm_left audio_to_modem_n audio_to_modem_p audio_irq audio_app_i2s_da_data audio_from_bt_pcm_data audio_pwr_amplifier_standby audio_to_bt_pcm_data audio_fm_left audio_fm_right audio_to_modem_p audio_to_modem_n audio_earkit_common_voltage_speaker audio_app_i2s_ad_data audio_app_i2s_ad_da_sync audio_app_i2s_ad_da_clk audio_fm_antenna audio_bt_pcm_fs audio_irq audio_pcm_clk audio_to_tvout_l audio_to_bt_pcm_data audio_pcm_clk 5 audio_1v8 5 audio_app_i2s_ad_da_sync audio_app_i2s_ad_da_clk audio_i2c_sclk audio_i2c_sda audio_clk audio_from_modem_p audio_from_modem_n 5 vbat audio_from_bt_pcm_data audio_bt_pcm_fs audio_app_i2s_ad_data audio_app_i2s_da_data audio_to_tvout_r audio_i2c_sclk audio_i2c_sda audio_clk audio_2v8 5 5 ordering information STW5098 84/85 20 ordering information 21 revision history table 59. order codes part number package packing STW5098 lfbga 6x6x1.4, 0.5 mm pitch, 112 pins tray STW5098t lfbga 6x6x1.4, 0.5 mm pitch, 112 pins tape and reel STW5098bblr/lf vfbga 5x5x1.0, 0.4 mm pitch, 112 pins tray STW5098bblt/lf vfbga 5x5x1.0, 0.4 mm pitch, 112 pins tape and reel table 60. document revision history date revision changes 24-apr-2007 1 initial release. STW5098 85/85 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in military, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2007 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com |
Price & Availability of STW5098
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |